X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=PcAtChipsetPkg%2FPciHostBridgeDxe%2FPciRootBridgeIo.c;h=edbe4a03b2a1d9bf2031fda802633724c913c9bc;hb=cac2ab9556d7cb0d658098a9df0b657d862a55d5;hp=11eadb40f76c876bbcd4daeaa3369fc83701f676;hpb=21b404d11e1e9f2577aad5105a784bbac6cdde55;p=mirror_edk2.git diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c old mode 100755 new mode 100644 index 11eadb40f7..edbe4a03b2 --- a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c @@ -1,14 +1,14 @@ /** @file PCI Root Bridge Io Protocol implementation - Copyright (c) 2008 - 2009, Intel Corporation
All rights - reserved. This program and the accompanying materials are - licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.
+This program and the accompanying materials are +licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ @@ -33,6 +33,35 @@ RESOURCE_CONFIGURATION Configuration = { // Protocol Member Function Prototypes // +/** + Polls an address in memory mapped I/O space until an exit condition is met, or + a timeout occurs. + + This function provides a standard way to poll a PCI memory location. A PCI memory read + operation is performed at the PCI memory address specified by Address for the width specified + by Width. The result of this PCI memory read operation is stored in Result. This PCI memory + read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result & + Mask) is equal to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the memory operations. The caller is + responsible for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask + are ignored. The bits in the bytes below Width which are zero in + Mask are ignored when polling the memory address. + @param[in] Value The comparison value used for the polling exit criteria. + @param[in] Delay The number of 100 ns units to poll. Note that timer available may + be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory location. + + @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoPollMem ( @@ -45,6 +74,35 @@ RootBridgeIoPollMem ( OUT UINT64 *Result ); +/** + Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is + satisfied or after a defined duration. + + This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is + performed at the PCI I/O address specified by Address for the width specified by Width. + The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is + repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal + to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the I/O operations. + @param[in] Address The base address of the I/O operations. The caller is responsible + for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask + are ignored. The bits in the bytes below Width which are zero in + Mask are ignored when polling the I/O address. + @param[in] Value The comparison value used for the polling exit criteria. + @param[in] Delay The number of 100 ns units to poll. Note that timer available may + be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory location. + + @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoPollIo ( @@ -57,6 +115,29 @@ RootBridgeIoPollIo ( OUT UINT64 *Result ); +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller + registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is responsible for satisfying + any alignment and memory width restrictions that a PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The caller is + responsible for aligning the Address if required. + @param[in] Count The number of memory operations to perform. Bytes moved is + Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoMemRead ( @@ -67,6 +148,28 @@ RootBridgeIoMemRead ( IN OUT VOID *Buffer ); +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller + registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is responsible for satisfying + any alignment and memory width restrictions that a PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The caller is + responsible for aligning the Address if required. + @param[in] Count The number of memory operations to perform. Bytes moved is + Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. +**/ EFI_STATUS EFIAPI RootBridgeIoMemWrite ( @@ -77,6 +180,24 @@ RootBridgeIoMemWrite ( IN OUT VOID *Buffer ); +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the I/O operation. The caller is responsible for + aligning the Address if required. + @param[in] Count The number of I/O operations to perform. Bytes moved is Width + size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoIoRead ( @@ -87,6 +208,24 @@ RootBridgeIoIoRead ( IN OUT VOID *UserBuffer ); +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the I/O operation. The caller is responsible for + aligning the Address if required. + @param[in] Count The number of I/O operations to perform. Bytes moved is Width + size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoIoWrite ( @@ -97,6 +236,30 @@ RootBridgeIoIoWrite ( IN OUT VOID *UserBuffer ); +/** + Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI + root bridge memory space. + + The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory + space to another region of PCI root bridge memory space. This is especially useful for video scroll + operation on a memory mapped video buffer. + The memory operations are carried out exactly as requested. The caller is responsible for satisfying + any alignment and memory width restrictions that a PCI root bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + @param[in] Width Signifies the width of the memory operations. + @param[in] DestAddress The destination address of the memory operation. The caller is + responsible for aligning the DestAddress if required. + @param[in] SrcAddress The source address of the memory operation. The caller is + responsible for aligning the SrcAddress if required. + @param[in] Count The number of memory operations to perform. Bytes moved is + Width size * Count, starting at DestAddress and SrcAddress. + + @retval EFI_SUCCESS The data was copied from one memory region to another memory region. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoCopyMem ( @@ -107,6 +270,29 @@ RootBridgeIoCopyMem ( IN UINTN Count ); +/** + Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space. + + The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration + registers for a PCI controller. + The PCI Configuration operations are carried out exactly as requested. The caller is responsible for + any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might + require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The address within the PCI configuration space for the PCI controller. + @param[in] Count The number of PCI configuration operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoPciRead ( @@ -117,6 +303,29 @@ RootBridgeIoPciRead ( IN OUT VOID *Buffer ); +/** + Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space. + + The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration + registers for a PCI controller. + The PCI Configuration operations are carried out exactly as requested. The caller is responsible for + any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might + require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The address within the PCI configuration space for the PCI controller. + @param[in] Count The number of PCI configuration operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoPciWrite ( @@ -127,6 +336,32 @@ RootBridgeIoPciWrite ( IN OUT VOID *Buffer ); +/** + Provides the PCI controller-specific addresses required to access system memory from a + DMA bus master. + + The Map() function provides the PCI controller specific addresses needed to access system + memory. This function is used to map system memory for PCI bus master DMA accesses. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Operation Indicates if the bus master is going to read or write to system memory. + @param[in] HostAddress The system memory address to map to the PCI controller. + @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped. + @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use + to access the system memory's HostAddress. + @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete. + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_INVALID_PARAMETER Operation is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL. + @retval EFI_INVALID_PARAMETER DeviceAddress is NULL. + @retval EFI_INVALID_PARAMETER Mapping is NULL. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. + @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoMap ( @@ -138,6 +373,22 @@ RootBridgeIoMap ( OUT VOID **Mapping ); +/** + Completes the Map() operation and releases any corresponding resources. + + The Unmap() function completes the Map() operation and releases any corresponding resources. + If the operation was an EfiPciOperationBusMasterWrite or + EfiPciOperationBusMasterWrite64, the data is committed to the target system memory. + Any resources used for the mapping are freed. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target system memory. + +**/ EFI_STATUS EFIAPI RootBridgeIoUnmap ( @@ -145,6 +396,27 @@ RootBridgeIoUnmap ( IN VOID *Mapping ); +/** + Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or + EfiPciOperationBusMasterCommonBuffer64 mapping. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Type This parameter is not used and must be ignored. + @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory address of the allocated range. + @param Attributes The requested bit mask of attributes for the allocated range. Only + the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, + and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_INVALID_PARAMETER MemoryType is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are + MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ EFI_STATUS EFIAPI RootBridgeIoAllocateBuffer ( @@ -156,6 +428,20 @@ RootBridgeIoAllocateBuffer ( IN UINT64 Attributes ); +/** + Frees memory that was allocated with AllocateBuffer(). + + The FreeBuffer() function frees memory that was allocated with AllocateBuffer(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages + was not allocated with AllocateBuffer(). + +**/ EFI_STATUS EFIAPI RootBridgeIoFreeBuffer ( @@ -164,12 +450,51 @@ RootBridgeIoFreeBuffer ( OUT VOID *HostAddress ); +/** + Flushes all PCI posted write transactions from a PCI host bridge to system memory. + + The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system + memory. Posted write transactions are generated by PCI bus masters when they perform write + transactions to target addresses in system memory. + This function does not flush posted write transactions from any PCI bridges. A PCI controller + specific action must be taken to guarantee that the posted write transactions have been flushed from + the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with + a PCI read transaction from the PCI controller prior to calling Flush(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + + @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host + bridge to system memory. + @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI + host bridge due to a hardware error. + +**/ EFI_STATUS EFIAPI RootBridgeIoFlush ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This ); +/** + Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the + attributes that a PCI root bridge is currently using. + + The GetAttributes() function returns the mask of attributes that this PCI root bridge supports + and the mask of attributes that the PCI root bridge is currently using. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Supported A pointer to the mask of attributes that this PCI root bridge + supports setting with SetAttributes(). + @param Attributes A pointer to the mask of attributes that this PCI root bridge is + currently using. + + @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root + bridge supports is returned in Supports. If Attributes is + not NULL, then the attributes that the PCI root bridge is currently + using is returned in Attributes. + @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. + +**/ EFI_STATUS EFIAPI RootBridgeIoGetAttributes ( @@ -178,6 +503,36 @@ RootBridgeIoGetAttributes ( OUT UINT64 *Attributes ); +/** + Sets attributes for a resource range on a PCI root bridge. + + The SetAttributes() function sets the attributes specified in Attributes for the PCI root + bridge on the resource range specified by ResourceBase and ResourceLength. Since the + granularity of setting these attributes may vary from resource type to resource type, and from + platform to platform, the actual resource range and the one passed in by the caller may differ. As a + result, this function may set the attributes specified by Attributes on a larger resource range + than the caller requested. The actual range is returned in ResourceBase and + ResourceLength. The caller is responsible for verifying that the actual range for which the + attributes were set is acceptable. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Attributes The mask of attributes to set. If the attribute bit + MEMORY_WRITE_COMBINE, MEMORY_CACHED, or + MEMORY_DISABLE is set, then the resource range is specified by + ResourceBase and ResourceLength. If + MEMORY_WRITE_COMBINE, MEMORY_CACHED, and + MEMORY_DISABLE are not set, then ResourceBase and + ResourceLength are ignored, and may be NULL. + @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified + by the attributes specified by Attributes. + @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the + attributes specified by Attributes. + + @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved. + @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + +**/ EFI_STATUS EFIAPI RootBridgeIoSetAttributes ( @@ -187,6 +542,29 @@ RootBridgeIoSetAttributes ( IN OUT UINT64 *ResourceLength ); +/** + Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0 + resource descriptors. + + There are only two resource descriptor types from the ACPI Specification that may be used to + describe the current resources allocated to a PCI root bridge. These are the QWORD Address + Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The + QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic + or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD + Address Space Descriptors followed by an End Tag. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the + current configuration of this PCI root bridge. The storage for the + ACPI 2.0 resource descriptors is allocated by this function. The + caller must treat the return buffer as read-only data, and the buffer + must not be freed by the caller. + + @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved. + @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + +**/ EFI_STATUS EFIAPI RootBridgeIoConfiguration ( @@ -195,24 +573,58 @@ RootBridgeIoConfiguration ( ); // -// Sub Function Prototypes +// Memory Controller Pci Root Bridge Io Module Variables // -EFI_STATUS -RootBridgeIoPciRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN BOOLEAN Write, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN OUT VOID *UserBuffer - ); +EFI_METRONOME_ARCH_PROTOCOL *mMetronome; // -// Memory Controller Pci Root Bridge Io Module Variables +// Lookup table for increment values based on transfer widths // -EFI_METRONOME_ARCH_PROTOCOL *mMetronome; -EFI_CPU_IO_PROTOCOL *mCpuIo; +UINT8 mInStride[] = { + 1, // EfiPciWidthUint8 + 2, // EfiPciWidthUint16 + 4, // EfiPciWidthUint32 + 8, // EfiPciWidthUint64 + 0, // EfiPciWidthFifoUint8 + 0, // EfiPciWidthFifoUint16 + 0, // EfiPciWidthFifoUint32 + 0, // EfiPciWidthFifoUint64 + 1, // EfiPciWidthFillUint8 + 2, // EfiPciWidthFillUint16 + 4, // EfiPciWidthFillUint32 + 8 // EfiPciWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mOutStride[] = { + 1, // EfiPciWidthUint8 + 2, // EfiPciWidthUint16 + 4, // EfiPciWidthUint32 + 8, // EfiPciWidthUint64 + 1, // EfiPciWidthFifoUint8 + 2, // EfiPciWidthFifoUint16 + 4, // EfiPciWidthFifoUint32 + 8, // EfiPciWidthFifoUint64 + 0, // EfiPciWidthFillUint8 + 0, // EfiPciWidthFillUint16 + 0, // EfiPciWidthFillUint32 + 0 // EfiPciWidthFillUint64 +}; + +/** + + Construct the Pci Root Bridge Io protocol + @param Protocol Point to protocol instance + @param HostBridgeHandle Handle of host bridge + @param Attri Attribute of host bridge + @param ResAppeture ResourceAppeture for host bridge + + @retval EFI_SUCCESS Success to initialize the Pci Root Bridge. + +**/ EFI_STATUS RootBridgeConstructor ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, @@ -220,21 +632,6 @@ RootBridgeConstructor ( IN UINT64 Attri, IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture ) -/*++ - -Routine Description: - - Construct the Pci Root Bridge Io protocol - -Arguments: - - Protocol - protocol to initialize - -Returns: - - None - ---*/ { EFI_STATUS Status; PCI_ROOT_BRIDGE_INSTANCE *PrivateData; @@ -272,8 +669,6 @@ Returns: PrivateData->ResAllocNode[Index].Status = ResNone; } - - EfiInitializeLock (&PrivateData->PciLock, TPL_HIGH_LEVEL); PrivateData->PciAddress = 0xCF8; PrivateData->PciData = 0xCFC; @@ -313,15 +708,420 @@ Returns: Protocol->SegmentNumber = 0; - Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (VOID **)&mCpuIo); - ASSERT_EFI_ERROR (Status); - Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome); ASSERT_EFI_ERROR (Status); return EFI_SUCCESS; } +/** + Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO. + + The I/O operations are carried out exactly as requested. The caller is responsible + for satisfying any alignment and I/O width restrictions that a PI System on a + platform might require. For example on some platforms, width requests of + EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will + be handled by the driver. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] OperationType I/O operation type: IO/MMIO/PCI. + @param[in] Width Signifies the width of the I/O or Memory operation. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The number of + bytes moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to store the results. + For write operations, the source buffer from which to write data. + + @retval EFI_SUCCESS The parameters for this request pass the checks. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. + @retval EFI_UNSUPPORTED The address range specified by Address, Width, + and Count is not valid for this PI system. + +**/ +EFI_STATUS +RootBridgeIoCheckParameter ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN OPERATION_TYPE OperationType, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr; + UINT64 MaxCount; + UINT64 Base; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if (Width < EfiPciWidthUint8 || Width >= EfiPciWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) { + Count = 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); + if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) { + return EFI_UNSUPPORTED; + } + + PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + // + // Check to see if any address associated with this transfer exceeds the maximum + // allowed address. The maximum address implied by the parameters passed in is + // Address + Size * Count. If the following condition is met, then the transfer + // is not supported. + // + // Address + Size * Count > Limit + 1 + // + // Since Limit can be the maximum integer value supported by the CPU and Count + // can also be the maximum integer value supported by the CPU, this range + // check must be adjusted to avoid all oveflow conditions. + // + // The following form of the range check is equivalent but assumes that + // Limit is of the form (2^n - 1). + // + if (OperationType == IoOperation) { + Base = PrivateData->IoBase; + Limit = PrivateData->IoLimit; + } else if (OperationType == MemOperation) { + Base = PrivateData->MemBase; + Limit = PrivateData->MemLimit; + } else { + PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address; + if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) { + return EFI_INVALID_PARAMETER; + } + + if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) { + return EFI_INVALID_PARAMETER; + } + + if (PciRbAddr->ExtendedRegister != 0) { + Address = PciRbAddr->ExtendedRegister; + } else { + Address = PciRbAddr->Register; + } + Base = 0; + Limit = MAX_PCI_REG_ADDRESS; + } + + if (Address < Base) { + return EFI_INVALID_PARAMETER; + } + + if (Count == 0) { + if (Address > Limit) { + return EFI_UNSUPPORTED; + } + } else { + MaxCount = RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return EFI_UNSUPPORTED; + } + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return EFI_UNSUPPORTED; + } + } + + return EFI_SUCCESS; +} + +/** + Internal help function for read and write memory space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Write Switch value for Read or Write. + @param[in] Width Signifies the width of the memory operations. + @param[in] UserAddress The address within the PCI configuration space for the PCI controller. + @param[in] Count The number of PCI configuration operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] UserBuffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +EFI_STATUS +RootBridgeIoMemRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + break; + case EfiPciWidthUint16: + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + break; + case EfiPciWidthUint32: + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + break; + case EfiPciWidthUint64: + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + *Uint8Buffer = MmioRead8 ((UINTN)Address); + break; + case EfiPciWidthUint16: + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address); + break; + case EfiPciWidthUint32: + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address); + break; + case EfiPciWidthUint64: + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); + break; + } + } + } + return EFI_SUCCESS; +} + +/** + Internal help function for read and write IO space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Write Switch value for Read or Write. + @param[in] Width Signifies the width of the memory operations. + @param[in] UserAddress The address within the PCI configuration space for the PCI controller. + @param[in] Count The number of PCI configuration operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] UserBuffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +EFI_STATUS +RootBridgeIoIoRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + IoWrite8 ((UINTN)Address, *Uint8Buffer); + break; + case EfiPciWidthUint16: + IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + break; + case EfiPciWidthUint32: + IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + *Uint8Buffer = IoRead8 ((UINTN)Address); + break; + case EfiPciWidthUint16: + *((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address); + break; + case EfiPciWidthUint32: + *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address); + break; + } + } + } + return EFI_SUCCESS; +} + +/** + Internal help function for read and write PCI configuration space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Write Switch value for Read or Write. + @param[in] Width Signifies the width of the memory operations. + @param[in] UserAddress The address within the PCI configuration space for the PCI controller. + @param[in] Count The number of PCI configuration operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] UserBuffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ +EFI_STATUS +RootBridgeIoPciRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr; + UINTN PcieRegAddr; + + Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address; + + PcieRegAddr = (UINTN) PCI_LIB_ADDRESS ( + PciRbAddr->Bus, + PciRbAddr->Device, + PciRbAddr->Function, + (PciRbAddr->ExtendedRegister != 0) ? \ + PciRbAddr->ExtendedRegister : + PciRbAddr->Register + ); + + InStride = mInStride[Width]; + OutStride = mOutStride[Width]; + OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); + for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + PciWrite8 (PcieRegAddr, *Uint8Buffer); + break; + case EfiPciWidthUint16: + PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer)); + break; + case EfiPciWidthUint32: + PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer)); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + *Uint8Buffer = PciRead8 (PcieRegAddr); + break; + case EfiPciWidthUint16: + *((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr); + break; + case EfiPciWidthUint32: + *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr); + break; + } + } + } + + return EFI_SUCCESS; +} + +/** + Polls an address in memory mapped I/O space until an exit condition is met, or + a timeout occurs. + + This function provides a standard way to poll a PCI memory location. A PCI memory read + operation is performed at the PCI memory address specified by Address for the width specified + by Width. The result of this PCI memory read operation is stored in Result. This PCI memory + read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result & + Mask) is equal to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the memory operations. The caller is + responsible for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask + are ignored. The bits in the bytes below Width which are zero in + Mask are ignored when polling the memory address. + @param[in] Value The comparison value used for the polling exit criteria. + @param[in] Delay The number of 100 ns units to poll. Note that timer available may + be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory location. + + @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoPollMem ( @@ -333,16 +1133,6 @@ RootBridgeIoPollMem ( IN UINT64 Delay, OUT UINT64 *Result ) -/*++ - -Routine Description: - Memory Poll - -Arguments: - -Returns: - ---*/ { EFI_STATUS Status; UINT64 NumberOfTicks; @@ -406,6 +1196,35 @@ Returns: return EFI_TIMEOUT; } +/** + Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is + satisfied or after a defined duration. + + This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is + performed at the PCI I/O address specified by Address for the width specified by Width. + The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is + repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal + to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the I/O operations. + @param[in] Address The base address of the I/O operations. The caller is responsible + for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask + are ignored. The bits in the bytes below Width which are zero in + Mask are ignored when polling the I/O address. + @param[in] Value The comparison value used for the polling exit criteria. + @param[in] Delay The number of 100 ns units to poll. Note that timer available may + be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory location. + + @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoPollIo ( @@ -417,16 +1236,6 @@ RootBridgeIoPollIo ( IN UINT64 Delay, OUT UINT64 *Result ) -/*++ - -Routine Description: - Io Poll - -Arguments: - -Returns: - ---*/ { EFI_STATUS Status; UINT64 NumberOfTicks; @@ -488,6 +1297,29 @@ Returns: return EFI_TIMEOUT; } +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller + registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is responsible for satisfying + any alignment and memory width restrictions that a PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The caller is + responsible for aligning the Address if required. + @param[in] Count The number of memory operations to perform. Bytes moved is + Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoMemRead ( @@ -497,55 +1329,32 @@ RootBridgeIoMemRead ( IN UINTN Count, IN OUT VOID *Buffer ) -/*++ - -Routine Description: - Memory read - -Arguments: - -Returns: - ---*/ { - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth; - UINTN OldCount; - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width < 0 || Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - // - // Check memory access limit - // - if (Address < PrivateData->MemBase) { - return EFI_INVALID_PARAMETER; - } - - OldWidth = Width; - OldCount = Count; - - if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) { - Count = 1; - } - - Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03); - - if (Address + (((UINTN)1 << Width) * Count) - 1 > PrivateData->MemLimit) { - return EFI_INVALID_PARAMETER; - } - - return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth, - Address, OldCount, Buffer); + return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer); } +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller + registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is responsible for satisfying + any alignment and memory width restrictions that a PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The caller is + responsible for aligning the Address if required. + @param[in] Count The number of memory operations to perform. Bytes moved is + Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. +**/ EFI_STATUS EFIAPI RootBridgeIoMemWrite ( @@ -555,54 +1364,28 @@ RootBridgeIoMemWrite ( IN UINTN Count, IN OUT VOID *Buffer ) -/*++ - -Routine Description: - Memory write - -Arguments: - -Returns: - ---*/ { - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth; - UINTN OldCount; - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width < 0 || Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - // - // Check memory access limit - // - if (Address < PrivateData->MemBase) { - return EFI_INVALID_PARAMETER; - } - - OldWidth = Width; - OldCount = Count; - if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) { - Count = 1; - } - - Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03); - - if (Address + (((UINTN)1 << Width) * Count) - 1 > PrivateData->MemLimit) { - return EFI_INVALID_PARAMETER; - } - - return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth, - Address, OldCount, Buffer); + return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer); } +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the I/O operation. The caller is responsible for + aligning the Address if required. + @param[in] Count The number of I/O operations to perform. Bytes moved is Width + size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoIoRead ( @@ -612,65 +1395,28 @@ RootBridgeIoIoRead ( IN UINTN Count, IN OUT VOID *Buffer ) -/*++ - -Routine Description: - Io read - -Arguments: - -Returns: - ---*/ { - - - UINTN AlignMask; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth; - UINTN OldCount; - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width < 0 || Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - //AlignMask = (1 << Width) - 1; - AlignMask = (1 << (Width & 0x03)) - 1; - - // - // check Io access limit - // - if (Address < PrivateData->IoBase) { - return EFI_INVALID_PARAMETER; - } - - OldWidth = Width; - OldCount = Count; - if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) { - Count = 1; - } - - Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03); - - if (Address + (((UINTN)1 << Width) * Count) - 1 >= PrivateData->IoLimit) { - return EFI_INVALID_PARAMETER; - } - - if (Address & AlignMask) { - return EFI_INVALID_PARAMETER; - } - - return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth, - Address, OldCount, Buffer); - + return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer); } +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the I/O operation. The caller is responsible for + aligning the Address if required. + @param[in] Count The number of I/O operations to perform. Bytes moved is Width + size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoIoWrite ( @@ -680,63 +1426,34 @@ RootBridgeIoIoWrite ( IN UINTN Count, IN OUT VOID *Buffer ) -/*++ - -Routine Description: - Io write - -Arguments: - -Returns: - ---*/ { - UINTN AlignMask; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth; - UINTN OldCount; - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width < 0 || Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - //AlignMask = (1 << Width) - 1; - AlignMask = (1 << (Width & 0x03)) - 1; - - // - // Check Io access limit - // - if (Address < PrivateData->IoBase) { - return EFI_INVALID_PARAMETER; - } - - OldWidth = Width; - OldCount = Count; - if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) { - Count = 1; - } - - Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03); - - if (Address + (((UINTN)1 << Width) * Count) - 1 >= PrivateData->IoLimit) { - return EFI_INVALID_PARAMETER; - } - - if (Address & AlignMask) { - return EFI_INVALID_PARAMETER; - } - - return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth, - Address, OldCount, Buffer); - + return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer); } +/** + Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI + root bridge memory space. + + The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory + space to another region of PCI root bridge memory space. This is especially useful for video scroll + operation on a memory mapped video buffer. + The memory operations are carried out exactly as requested. The caller is responsible for satisfying + any alignment and memory width restrictions that a PCI root bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance. + @param[in] Width Signifies the width of the memory operations. + @param[in] DestAddress The destination address of the memory operation. The caller is + responsible for aligning the DestAddress if required. + @param[in] SrcAddress The source address of the memory operation. The caller is + responsible for aligning the SrcAddress if required. + @param[in] Count The number of memory operations to perform. Bytes moved is + Width size * Count, starting at DestAddress and SrcAddress. + + @retval EFI_SUCCESS The data was copied from one memory region to another memory region. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoCopyMem ( @@ -746,16 +1463,6 @@ RootBridgeIoCopyMem ( IN UINT64 SrcAddress, IN UINTN Count ) -/*++ - -Routine Description: - Memory copy - -Arguments: - -Returns: - ---*/ { EFI_STATUS Status; BOOLEAN Direction; @@ -812,6 +1519,29 @@ Returns: return EFI_SUCCESS; } +/** + Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space. + + The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration + registers for a PCI controller. + The PCI Configuration operations are carried out exactly as requested. The caller is responsible for + any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might + require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The address within the PCI configuration space for the PCI controller. + @param[in] Count The number of PCI configuration operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoPciRead ( @@ -821,31 +1551,33 @@ RootBridgeIoPciRead ( IN UINTN Count, IN OUT VOID *Buffer ) -/*++ - -Routine Description: - Pci read - -Arguments: - -Returns: - ---*/ { - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width < 0 || Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - // - // Read Pci configuration space - // return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer); } +/** + Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space. + + The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration + registers for a PCI controller. + The PCI Configuration operations are carried out exactly as requested. The caller is responsible for + any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might + require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The address within the PCI configuration space for the PCI controller. + @param[in] Count The number of PCI configuration operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to store the results. For + write operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoPciWrite ( @@ -855,31 +1587,36 @@ RootBridgeIoPciWrite ( IN UINTN Count, IN OUT VOID *Buffer ) -/*++ - -Routine Description: - Pci write - -Arguments: - -Returns: - ---*/ { - - if (Buffer == NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width < 0 || Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - // - // Write Pci configuration space - // return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer); } +/** + Provides the PCI controller-specific addresses required to access system memory from a + DMA bus master. + + The Map() function provides the PCI controller specific addresses needed to access system + memory. This function is used to map system memory for PCI bus master DMA accesses. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Operation Indicates if the bus master is going to read or write to system memory. + @param[in] HostAddress The system memory address to map to the PCI controller. + @param[in][out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped. + @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use + to access the system memory's HostAddress. + @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete. + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_INVALID_PARAMETER Operation is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL. + @retval EFI_INVALID_PARAMETER DeviceAddress is NULL. + @retval EFI_INVALID_PARAMETER Mapping is NULL. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. + @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ EFI_STATUS EFIAPI RootBridgeIoMap ( @@ -890,7 +1627,6 @@ RootBridgeIoMap ( OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, OUT VOID **Mapping ) - { EFI_STATUS Status; EFI_PHYSICAL_ADDRESS PhysicalAddress; @@ -999,13 +1735,28 @@ RootBridgeIoMap ( return EFI_SUCCESS; } +/** + Completes the Map() operation and releases any corresponding resources. + + The Unmap() function completes the Map() operation and releases any corresponding resources. + If the operation was an EfiPciOperationBusMasterWrite or + EfiPciOperationBusMasterWrite64, the data is committed to the target system memory. + Any resources used for the mapping are freed. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target system memory. + +**/ EFI_STATUS EFIAPI RootBridgeIoUnmap ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, IN VOID *Mapping ) - { MAP_INFO *MapInfo; @@ -1041,6 +1792,27 @@ RootBridgeIoUnmap ( return EFI_SUCCESS; } +/** + Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or + EfiPciOperationBusMasterCommonBuffer64 mapping. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Type This parameter is not used and must be ignored. + @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory address of the allocated range. + @param Attributes The requested bit mask of attributes for the allocated range. Only + the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, + and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_INVALID_PARAMETER MemoryType is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are + MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ EFI_STATUS EFIAPI RootBridgeIoAllocateBuffer ( @@ -1051,7 +1823,6 @@ RootBridgeIoAllocateBuffer ( OUT VOID **HostAddress, IN UINT64 Attributes ) - { EFI_STATUS Status; EFI_PHYSICAL_ADDRESS PhysicalAddress; @@ -1092,6 +1863,20 @@ RootBridgeIoAllocateBuffer ( return EFI_SUCCESS; } +/** + Frees memory that was allocated with AllocateBuffer(). + + The FreeBuffer() function frees memory that was allocated with AllocateBuffer(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages + was not allocated with AllocateBuffer(). + +**/ EFI_STATUS EFIAPI RootBridgeIoFreeBuffer ( @@ -1099,25 +1884,34 @@ RootBridgeIoFreeBuffer ( IN UINTN Pages, OUT VOID *HostAddress ) - { return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages); } +/** + Flushes all PCI posted write transactions from a PCI host bridge to system memory. + + The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system + memory. Posted write transactions are generated by PCI bus masters when they perform write + transactions to target addresses in system memory. + This function does not flush posted write transactions from any PCI bridges. A PCI controller + specific action must be taken to guarantee that the posted write transactions have been flushed from + the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with + a PCI read transaction from the PCI controller prior to calling Flush(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + + @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host + bridge to system memory. + @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI + host bridge due to a hardware error. + +**/ EFI_STATUS EFIAPI RootBridgeIoFlush ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This ) -/*++ - -Routine Description: - -Arguments: - -Returns: - ---*/ { // // not supported yet @@ -1125,6 +1919,26 @@ Returns: return EFI_SUCCESS; } +/** + Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the + attributes that a PCI root bridge is currently using. + + The GetAttributes() function returns the mask of attributes that this PCI root bridge supports + and the mask of attributes that the PCI root bridge is currently using. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Supported A pointer to the mask of attributes that this PCI root bridge + supports setting with SetAttributes(). + @param Attributes A pointer to the mask of attributes that this PCI root bridge is + currently using. + + @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root + bridge supports is returned in Supports. If Attributes is + not NULL, then the attributes that the PCI root bridge is currently + using is returned in Attributes. + @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. + +**/ EFI_STATUS EFIAPI RootBridgeIoGetAttributes ( @@ -1132,15 +1946,6 @@ RootBridgeIoGetAttributes ( OUT UINT64 *Supported, OUT UINT64 *Attributes ) -/*++ - -Routine Description: - -Arguments: - -Returns: - ---*/ { PCI_ROOT_BRIDGE_INSTANCE *PrivateData; @@ -1164,6 +1969,36 @@ Returns: return EFI_SUCCESS; } +/** + Sets attributes for a resource range on a PCI root bridge. + + The SetAttributes() function sets the attributes specified in Attributes for the PCI root + bridge on the resource range specified by ResourceBase and ResourceLength. Since the + granularity of setting these attributes may vary from resource type to resource type, and from + platform to platform, the actual resource range and the one passed in by the caller may differ. As a + result, this function may set the attributes specified by Attributes on a larger resource range + than the caller requested. The actual range is returned in ResourceBase and + ResourceLength. The caller is responsible for verifying that the actual range for which the + attributes were set is acceptable. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Attributes The mask of attributes to set. If the attribute bit + MEMORY_WRITE_COMBINE, MEMORY_CACHED, or + MEMORY_DISABLE is set, then the resource range is specified by + ResourceBase and ResourceLength. If + MEMORY_WRITE_COMBINE, MEMORY_CACHED, and + MEMORY_DISABLE are not set, then ResourceBase and + ResourceLength are ignored, and may be NULL. + @param[in][out] ResourceBase A pointer to the base address of the resource range to be modified + by the attributes specified by Attributes. + @param[in][out] ResourceLength A pointer to the length of the resource range to be modified by the + attributes specified by Attributes. + + @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved. + @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + +**/ EFI_STATUS EFIAPI RootBridgeIoSetAttributes ( @@ -1172,15 +2007,6 @@ RootBridgeIoSetAttributes ( IN OUT UINT64 *ResourceBase, IN OUT UINT64 *ResourceLength ) -/*++ - -Routine Description: - -Arguments: - -Returns: - ---*/ { PCI_ROOT_BRIDGE_INSTANCE *PrivateData; @@ -1205,21 +2031,35 @@ Returns: return EFI_SUCCESS; } +/** + Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0 + resource descriptors. + + There are only two resource descriptor types from the ACPI Specification that may be used to + describe the current resources allocated to a PCI root bridge. These are the QWORD Address + Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The + QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic + or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD + Address Space Descriptors followed by an End Tag. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the + current configuration of this PCI root bridge. The storage for the + ACPI 2.0 resource descriptors is allocated by this function. The + caller must treat the return buffer as read-only data, and the buffer + must not be freed by the caller. + + @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved. + @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + +**/ EFI_STATUS EFIAPI RootBridgeIoConfiguration ( IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, OUT VOID **Resources ) -/*++ - -Routine Description: - -Arguments: - -Returns: - ---*/ { PCI_ROOT_BRIDGE_INSTANCE *PrivateData; UINTN Index; @@ -1238,93 +2078,3 @@ Returns: return EFI_SUCCESS; } -// -// Internal function -// -EFI_STATUS -RootBridgeIoPciRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN BOOLEAN Write, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN OUT VOID *UserBuffer - ) -{ - PCI_CONFIG_ACCESS_CF8 Pci; - PCI_CONFIG_ACCESS_CF8 PciAligned; - UINT32 InStride; - UINT32 OutStride; - UINTN PciData; - UINTN PciDataStride; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress; - - if (Width < 0 || Width >= EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if ((Width & 0x03) >= EfiPciWidthUint64) { - return EFI_INVALID_PARAMETER; - } - - PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - InStride = 1 << (Width & 0x03); - OutStride = InStride; - if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) { - InStride = 0; - } - - if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) { - OutStride = 0; - } - - CopyMem (&PciAddress, &UserAddress, sizeof(UINT64)); - - if (PciAddress.ExtendedRegister > 0xFF) { - return EFI_UNSUPPORTED; - } - - if (PciAddress.ExtendedRegister != 0) { - Pci.Bits.Reg = PciAddress.ExtendedRegister & 0xFF; - } else { - Pci.Bits.Reg = PciAddress.Register; - } - - Pci.Bits.Func = PciAddress.Function; - Pci.Bits.Dev = PciAddress.Device; - Pci.Bits.Bus = PciAddress.Bus; - Pci.Bits.Reserved = 0; - Pci.Bits.Enable = 1; - - // - // PCI Config access are all 32-bit alligned, but by accessing the - // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types - // are possible on PCI. - // - // To read a byte of PCI config space you load 0xcf8 and - // read 0xcfc, 0xcfd, 0xcfe, 0xcff - // - PciDataStride = Pci.Bits.Reg & 0x03; - - while (Count) { - CopyMem (&PciAligned, &Pci, sizeof (PciAligned)); - PciAligned.Bits.Reg &= 0xfc; - PciData = (UINTN)PrivateData->PciData + PciDataStride; - EfiAcquireLock(&PrivateData->PciLock); - This->Io.Write (This, EfiPciWidthUint32, PrivateData->PciAddress, 1, &PciAligned); - if (Write) { - This->Io.Write (This, Width, PciData, 1, UserBuffer); - } else { - This->Io.Read (This, Width, PciData, 1, UserBuffer); - } - EfiReleaseLock(&PrivateData->PciLock); - UserBuffer = ((UINT8 *)UserBuffer) + OutStride; - PciDataStride = (PciDataStride + InStride) % 4; - Pci.Bits.Reg += InStride; - Count -= 1; - } - - return EFI_SUCCESS; -}