X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=UefiCpuPkg%2FCpuDxe%2FCpuGdt.c;fp=UefiCpuPkg%2FCpuDxe%2FCpuGdt.c;h=8847bc4819ca0f31cee9be69fbfc3203cbdd5e1c;hb=773b0bc2838ede154c6de9d78401b91fafa91062;hp=a1ab543f2da571e66b548a8f3c80713e34fed31a;hpb=030ba3097a6e7d08b99f8a9d19a322f61409c1f6;p=mirror_edk2.git diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index a1ab543f2d..8847bc4819 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -2,7 +2,7 @@ C based implementation of IA32 interrupt handling only requiring a minimal assembly interrupt entry point. - Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -13,7 +13,7 @@ // // Global descriptor table (GDT) Template // -STATIC GDT_ENTRIES GdtTemplate = { +STATIC GDT_ENTRIES mGdtTemplate = { // // NULL_SEL // @@ -124,27 +124,27 @@ InitGlobalDescriptorTable ( VOID ) { - GDT_ENTRIES *gdt; - IA32_DESCRIPTOR gdtPtr; + GDT_ENTRIES *Gdt; + IA32_DESCRIPTOR Gdtr; // // Allocate Runtime Data for the GDT // - gdt = AllocateRuntimePool (sizeof (GdtTemplate) + 8); - ASSERT (gdt != NULL); - gdt = ALIGN_POINTER (gdt, 8); + Gdt = AllocateRuntimePool (sizeof (mGdtTemplate) + 8); + ASSERT (Gdt != NULL); + Gdt = ALIGN_POINTER (Gdt, 8); // // Initialize all GDT entries // - CopyMem (gdt, &GdtTemplate, sizeof (GdtTemplate)); + CopyMem (Gdt, &mGdtTemplate, sizeof (mGdtTemplate)); // // Write GDT register // - gdtPtr.Base = (UINT32)(UINTN)(VOID*) gdt; - gdtPtr.Limit = (UINT16) (sizeof (GdtTemplate) - 1); - AsmWriteGdtr (&gdtPtr); + Gdtr.Base = (UINT32) (UINTN) Gdt; + Gdtr.Limit = (UINT16) (sizeof (mGdtTemplate) - 1); + AsmWriteGdtr (&Gdtr); // // Update selector (segment) registers base on new GDT @@ -152,4 +152,3 @@ InitGlobalDescriptorTable ( SetCodeSelector ((UINT16)CPU_CODE_SEL); SetDataSelectors ((UINT16)CPU_DATA_SEL); } -