X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=UefiCpuPkg%2FInclude%2FRegister%2FMsr%2FIvyBridgeMsr.h;h=f45b538ea7087ba44b599d78d03fa5a723f5320c;hb=ba1a2d1102de42b66b16e5e3152afb21447010b2;hp=39b0d1af12f92f982a9afc3e511076053877e49d;hpb=447b08b3d2a3e04a9fccda68c72a2ff62d8197e9;p=mirror_edk2.git

diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
index 39b0d1af12..f45b538ea7 100644
--- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -16,8 +16,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Specification Reference:
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
-  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10.
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
 
 **/
 
@@ -1112,7 +1112,7 @@ typedef union {
 
 
 /**
-  Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).".
+  Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
 
   @param  ECX  MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
   @param  EAX  Lower 32-bits of MSR value.