X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=UefiCpuPkg%2FUefiCpuPkg.dec;h=45b267ac61d5cf713f9dc2a09fb3a765ff2861e3;hb=08a475df10b75f84cdeb9b11e38f8eee9b5c048d;hp=14ddaa8633c62cf587a332f9278b59637054d9aa;hpb=ebfbb70129a84471b5165817acc38024443eaa47;p=mirror_edk2.git
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 14ddaa8633..45b267ac61 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -63,6 +63,9 @@
## Include/Guid/CpuFeaturesInitDone.h
gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
+ ## Include/Guid/MicrocodePatchHob.h
+ gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
+
[Protocols]
## Include/Protocol/SmmCpuService.h
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
@@ -81,7 +84,8 @@
[PcdsFeatureFlag]
## Indicates if SMM Profile will be enabled.
# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
- # It could not be enabled at the same time with SMM static page table feature (PcdCpuSmmStaticPageTable).
+ # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
+ # In IA32 build, the page table memory is not marked as read-only when it is enabled.
# This PCD is only for validation purpose. It should be set to false in production.
# TRUE - SMM Profile will be enabled.
# FALSE - SMM Profile will be disabled.
@@ -147,6 +151,10 @@
# @Prompt Specify size of good stack of exception which need switching stack.
gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
+ ## Count of pre allocated SMM MP tokens per chunk.
+ # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002
+
[PcdsFixedAtBuild, PcdsPatchableInModule]
## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
# @Prompt Configure base address of CPU Local APIC
@@ -211,6 +219,14 @@
# @Prompt If CPU features will be initialized during S3 resume.
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D
+ ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
+ # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
+ # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
+ # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
+ # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
+ # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113
+
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## Specifies max supported number of Logical Processors.
# @Prompt Configure max supported number of Logical Processors
@@ -218,6 +234,19 @@
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
# @Prompt Timeout for the BSP to detect all APs for the first time.
gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004
+ ## Specifies the number of Logical Processors that are available in the
+ # preboot environment after platform reset, including BSP and APs. Possible
+ # values:
+ # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
+ # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
+ # detection by the BSP.
+ # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
+ # AP detection finishes only when the detected CPU count
+ # (BSP plus APs) reaches the value of
+ # PcdCpuBootLogicalProcessorNumber, regardless of how long
+ # that takes.
+ # @Prompt Number of Logical Processors available after platform reset.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008
## Specifies the base address of the first microcode Patch in the microcode Region.
# @Prompt Microcode Region base address.
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005
@@ -238,17 +267,6 @@
# @Prompt The specified AP target C-state for Mwait.
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007
- ## Indicates if SMM uses static page table.
- # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.
- # This flag only impacts X64 build, because SMM always builds static page table for IA32.
- # It could not be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
- # It could not be enabled also at the same time with heap guard feature for SMM
- # (PcdHeapGuardPropertyMask in MdeModulePkg).
- # TRUE - SMM uses static page table for all memory.
- # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.
- # @Prompt Use static page table for all memory in SMM.
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D
-
## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
# @Prompt AP synchronization timeout value in SMM.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
@@ -270,6 +288,23 @@
# @Prompt Current boot is a power-on reset.
gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B
+[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
+ ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
+ # MMIO access is always allowed regardless of the value of this PCD.
+ # Loose of such restriction is only required by RAS components in X64 platforms.
+ # The PCD value is considered as constantly TRUE in IA32 platforms.
+ # When the PCD value is TRUE, page table is initialized to cover all memory spaces
+ # and the memory occupied by page table is protected by page table itself as read-only.
+ # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
+ # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
+ # (PcdHeapGuardPropertyMask in MdeModulePkg).
+ # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
+ # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
+ # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
+ # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.
+ # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
+
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.