X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=UefiCpuPkg%2FUefiCpuPkg.dec;h=762badf5d2396f938438c6cbcdf3d4c3d7ba1339;hb=a1c35ff312efb1452427e695d58fb1f26b67661e;hp=4a679bdb5700be98e6ea9e1378309f97f11c47aa;hpb=82e75ac65abdfca034cfb38edcee8a7cbc6e6271;p=mirror_edk2.git
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 4a679bdb57..762badf5d2 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -1,15 +1,9 @@
## @file UefiCpuPkg.dec
# This Package provides UEFI compatible CPU modules and libraries.
#
-# Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
#
-# This program and the accompanying materials are licensed and made available under
-# the terms and conditions of the BSD License which accompanies this distribution.
-# The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -18,7 +12,7 @@
PACKAGE_NAME = UefiCpuPkg
PACKAGE_UNI_FILE = UefiCpuPkg.uni
PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
- PACKAGE_VERSION = 0.3
+ PACKAGE_VERSION = 0.90
[Includes]
Include
@@ -32,7 +26,7 @@
## @libraryclass Defines some routines that are used to register/manage/program
## CPU features.
##
- UefiCpuLib|Include/Library/RegisterCpuFeaturesLib.h
+ RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h
[LibraryClasses.IA32, LibraryClasses.X64]
## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
@@ -59,23 +53,19 @@
##
MpInitLib|Include/Library/MpInitLib.h
- ## @libraryclass Provides services to access Microcode region on flash device.
- #
- MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h
-
[Guids]
gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
- ## Include/Guid/MicrocodeFmp.h
- gMicrocodeFmpImageTypeIdGuid = { 0x96d4fdcd, 0x1502, 0x424d, { 0x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } }
-
## Include/Guid/CpuFeaturesSetDone.h
gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
## Include/Guid/CpuFeaturesInitDone.h
gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
+ ## Include/Guid/MicrocodePatchHob.h
+ gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
+
[Protocols]
## Include/Protocol/SmmCpuService.h
gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
@@ -88,9 +78,17 @@
# 0x80000001 | Invalid value provided.
#
+[Ppis]
+ gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}
+
+ ## Include/Ppi/ShadowMicrocode.h
+ gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}
+
[PcdsFeatureFlag]
## Indicates if SMM Profile will be enabled.
# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
+ # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
+ # In IA32 build, the page table memory is not marked as read-only when it is enabled.
# This PCD is only for validation purpose. It should be set to false in production.
# TRUE - SMM Profile will be enabled.
# FALSE - SMM Profile will be disabled.
@@ -144,6 +142,22 @@
# @Prompt Lock SMM Feature Control MSR.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
+[PcdsFixedAtBuild]
+ ## List of exception vectors which need switching stack.
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.
+ # By default exception #DD(8), #PF(14) are supported.
+ # @Prompt Specify exception vectors which need switching stack.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000
+
+ ## Size of good stack for an exception.
+ # This PCD will only take into effect if PcdCpuStackGuard is enabled.
+ # @Prompt Specify size of good stack of exception which need switching stack.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
+
+ ## Count of pre allocated SMM MP tokens per chunk.
+ # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002
+
[PcdsFixedAtBuild, PcdsPatchableInModule]
## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
# @Prompt Configure base address of CPU Local APIC
@@ -171,6 +185,10 @@
# @Prompt Processor stack size in SMM.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
+ ## Specifies shadow stack size in bytes for each processor in SMM.
+ # @Prompt Processor shadow stack size in SMM.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E
+
## Indicates if SMM Code Access Check is enabled.
# If enabled, the SMM handler cannot execute the code outside SMM regions.
# This PCD is suggested to TRUE in production image.
@@ -192,18 +210,32 @@
# @Prompt MSEG size.
gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112
- ## Specifies the supported CPU features bit in array
- # @Prompt Supported CPU features
+ ## Specifies the supported CPU features bit in array.
+ # @Prompt Supported CPU features.
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016
- ## Specifies if CPU features will be initialized after SMM relocation
- # @Prompt if CPU features will be initialized after SMM relocation
+ ## Specifies if CPU features will be initialized after SMM relocation.
+ # @Prompt If CPU features will be initialized after SMM relocation.
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C
- ## Specifies if CPU features will be initialized during S3 resume
- # @Prompt if CPU features will be initialized during S3 resume
+ ## Specifies if CPU features will be initialized during S3 resume.
+ # @Prompt If CPU features will be initialized during S3 resume.
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D
+ ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
+ # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
+ # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
+ # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
+ # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
+ # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113
+
+ ## Specifies the periodic interval value in microseconds for the status check
+ # of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking
+ # mode in DXE phase.
+ # @Prompt Periodic interval value in microseconds for AP status check in DXE.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E
+
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## Specifies max supported number of Logical Processors.
# @Prompt Configure max supported number of Logical Processors
@@ -211,6 +243,19 @@
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
# @Prompt Timeout for the BSP to detect all APs for the first time.
gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004
+ ## Specifies the number of Logical Processors that are available in the
+ # preboot environment after platform reset, including BSP and APs. Possible
+ # values:
+ # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
+ # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
+ # detection by the BSP.
+ # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
+ # AP detection finishes only when the detected CPU count
+ # (BSP plus APs) reaches the value of
+ # PcdCpuBootLogicalProcessorNumber, regardless of how long
+ # that takes.
+ # @Prompt Number of Logical Processors available after platform reset.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008
## Specifies the base address of the first microcode Patch in the microcode Region.
# @Prompt Microcode Region base address.
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005
@@ -231,14 +276,6 @@
# @Prompt The specified AP target C-state for Mwait.
gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007
- ## Indicates if SMM uses static page table.
- # If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory.
- # This flag only impacts X64 build, because SMM alway builds static page table for IA32.
- # TRUE - SMM uses static page table for all memory.
- # FALSE - SMM uses static page table for below 4G memory and use on-demand paging for above 4G memory.
- # @Prompt Use static page table for all memory in SMM.
- gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x3213210D
-
## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
# @Prompt AP synchronization timeout value in SMM.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
@@ -249,10 +286,6 @@
# @Prompt SMM CPU Synchronization Method.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014
- ## Specifies user's desired settings for enabling/disabling processor features.
- # @Prompt User settings for enabling/disabling processor features.
- gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesUserConfiguration|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000017
-
## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
# @Prompt The encoded values for target duty cycle modulation.
# @ValidRange 0x80000001 | 0 - 15
@@ -264,6 +297,23 @@
# @Prompt Current boot is a power-on reset.
gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B
+[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
+ ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
+ # MMIO access is always allowed regardless of the value of this PCD.
+ # Loose of such restriction is only required by RAS components in X64 platforms.
+ # The PCD value is considered as constantly TRUE in IA32 platforms.
+ # When the PCD value is TRUE, page table is initialized to cover all memory spaces
+ # and the memory occupied by page table is protected by page table itself as read-only.
+ # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
+ # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
+ # (PcdHeapGuardPropertyMask in MdeModulePkg).
+ # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
+ # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
+ # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
+ # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.
+ # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
+
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.
@@ -280,10 +330,45 @@
# @ValidList 0x80000001 | 0
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018
- ## Specifies actual settings for processor features, each bit corresponding to a specific feature.
- # @Prompt Actual processor feature settings.
+ ## As input, specifies user's desired settings for enabling/disabling processor features.
+ ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
+ # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
# @ValidList 0x80000001 | 0
gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019
+ ## Contains the size of memory required when CPU processor trace is enabled.
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.
+ # This PCD is ignored if CPU processor trace is disabled.
+ # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.
+ # 0x0 - 4K.
+ # 0x1 - 8K.
+ # 0x2 - 16K.
+ # 0x3 - 32K.
+ # 0x4 - 64K.
+ # 0x5 - 128K.
+ # 0x6 - 256K.
+ # 0x7 - 512K.
+ # 0x8 - 1M.
+ # 0x9 - 2M.
+ # 0xA - 4M.
+ # 0xB - 8M.
+ # 0xC - 16M.
+ # 0xD - 32M.
+ # 0xE - 64M.
+ # 0xF - 128M.
+ # @Prompt The memory size used for processor trace if processor trace is enabled.
+ # @ValidRange 0x80000001 | 0 - 0xF
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012
+
+ ## Contains the processor trace output scheme when CPU processor trace is enabled.
+ # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.
+ # This PCD is ignored if CPU processor trace is disabled.
+ # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.
+ # 0 - Single Range output scheme.
+ # 1 - ToPA(Table of physical address) scheme.
+ # @Prompt The processor trace output scheme used when processor trace is enabled.
+ # @ValidRange 0x80000001 | 0 - 1
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015
+
[UserExtensions.TianoCore."ExtraFiles"]
UefiCpuPkgExtra.uni