X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=UefiCpuPkg%2FUefiCpuPkg.uni;h=2db49e841b4ac862a93e7978893797f57b0abf42;hb=dd01704111c6e85b7bca62968d48abc2c626a3c6;hp=6a6890d07499dc3abb0f1f55b92a80bee680fa71;hpb=792396bec9192b0bd3c3584e5705201facd1a5ef;p=mirror_edk2.git diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index 6a6890d074..2db49e841b 100644 --- a/UefiCpuPkg/UefiCpuPkg.uni +++ b/UefiCpuPkg/UefiCpuPkg.uni @@ -5,13 +5,7 @@ // // Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.
// -// This program and the accompanying materials are licensed and made available under -// the terms and conditions of the BSD License which accompanies this distribution. -// The full text of the license may be found at -// http://opensource.org/licenses/bsd-license.php -// -// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// SPDX-License-Identifier: BSD-2-Clause-Patent // // **/ @@ -43,6 +37,10 @@ #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApInitTimeOutInMicroSeconds_HELP #language en-US "Specifies timeout value in microseconds for the BSP to detect all APs for the first time." +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuBootLogicalProcessorNumber_PROMPT #language en-US "Number of Logical Processors available after platform reset." + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuBootLogicalProcessorNumber_HELP #language en-US "Specifies the number of Logical Processors that are available in the preboot environment after platform reset, including BSP and APs." + #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuMicrocodePatchAddress_PROMPT #language en-US "Microcode Region base address." #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuMicrocodePatchAddress_HELP #language en-US "Specifies the base address of the first microcode Patch in the microcode Region." @@ -102,6 +100,12 @@ "TRUE - locked.
\n" "FALSE - unlocked.
" +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuShadowMicrocodeByFit_PROMPT #language en-US "FIT based microcode shadowing" + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuShadowMicrocodeByFit_HELP #language en-US "Indicates if FIT based microcode shadowing will be enabled.

\n" + "TRUE - FIT base microcode shadowing will be enabled.
\n" + "FALSE - FIT base microcode shadowing will be disabled.
" + #string STR_gUefiCpuPkgTokenSpaceGuid_PcdPeiTemporaryRamStackSize_PROMPT #language en-US "Stack size in the temporary RAM" #string STR_gUefiCpuPkgTokenSpaceGuid_PcdPeiTemporaryRamStackSize_HELP #language en-US "Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize." @@ -197,6 +201,22 @@ #string STR_gUefiCpuPkgTokenSpaceGuid_PcdIsPowerOnReset_HELP #language en-US "Indicates if the current boot is a power-on reset." +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmRestrictedMemoryAccess_PROMPT #language en-US "Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock." + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmRestrictedMemoryAccess_HELP #language en-US "Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.

\n" + "MMIO access is always allowed regardless of the value of this PCD.
\n" + "Loose of such restriction is only required by RAS components in X64 platforms.
\n" + "The PCD value is considered as constantly TRUE in IA32 platforms.
\n" + "When the PCD value is TRUE, page table is initialized to cover all memory spaces
\n" + "and the memory occupied by page table is protected by page table itself as read-only.
\n" + "In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
\n" + "In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
\n" + "(PcdHeapGuardPropertyMask in MdeModulePkg).
\n" + "In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
\n" + "or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
\n" + "TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
\n" + "FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.
" + #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesCapability_PROMPT #language en-US "Processor feature capabilities." #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuFeaturesCapability_HELP #language en-US "Indicates processor feature capabilities, each bit corresponding to a specific feature." @@ -248,3 +268,16 @@ #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuKnownGoodStackSize_HELP #language en-US "Size of good stack for an exception.\n" "This PCD will only take into effect if PcdCpuStackGuard is enabled.\n" +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuCoreCrystalClockFrequency_PROMPT #language en-US "Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency." + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuCoreCrystalClockFrequency_HELP #language en-US "Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.

\n" + "TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.

\n" + "This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX.

\n" + "Default value is 24000000 for 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family.
\n" + "25000000 - Intel Xeon Processor Scalable Family with CPUID signature 06_55H(25MHz).
\n" + "24000000 - 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family(24MHz).
\n" + "19200000 - Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH(19.2MHz).
\n" + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmMpTokenCountPerChunk_PROMPT #language en-US "Specify the count of pre allocated SMM MP tokens per chunk.\n" + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuSmmMpTokenCountPerChunk_HELP #language en-US "This value used to specify the count of pre allocated SMM MP tokens per chunk.\n"