X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=cputlb.c;h=aba7e44e1e424fa618272e39b4607d92c5d56839;hb=refs%2Ftags%2Fv1.5.0;hp=0d1e2527fb0b761431cd62fda55b5d4ad3b6412b;hpb=77f4c9a68aedb9b0d290a1def1bfc8714be862ec;p=qemu.git diff --git a/cputlb.c b/cputlb.c index 0d1e2527f..aba7e44e1 100644 --- a/cputlb.c +++ b/cputlb.c @@ -19,13 +19,13 @@ #include "config.h" #include "cpu.h" -#include "exec-all.h" -#include "memory.h" +#include "exec/exec-all.h" +#include "exec/memory.h" +#include "exec/address-spaces.h" -#include "cputlb.h" +#include "exec/cputlb.h" -#define WANT_EXEC_OBSOLETE -#include "exec-obsolete.h" +#include "exec/memory-internal.h" //#define DEBUG_TLB //#define DEBUG_TLB_CHECK @@ -54,6 +54,7 @@ static const CPUTLBEntry s_cputlb_empty_entry = { */ void tlb_flush(CPUArchState *env, int flush_global) { + CPUState *cpu = ENV_GET_CPU(env); int i; #if defined(DEBUG_TLB) @@ -61,7 +62,7 @@ void tlb_flush(CPUArchState *env, int flush_global) #endif /* must reset current TB so that interrupts cannot modify the links while we are modifying them */ - env->current_tb = NULL; + cpu->current_tb = NULL; for (i = 0; i < CPU_TLB_SIZE; i++) { int mmu_idx; @@ -92,6 +93,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) void tlb_flush_page(CPUArchState *env, target_ulong addr) { + CPUState *cpu = ENV_GET_CPU(env); int i; int mmu_idx; @@ -110,7 +112,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr) } /* must reset current TB so that interrupts cannot modify the links while we are modifying them */ - env->current_tb = NULL; + cpu->current_tb = NULL; addr &= TARGET_PAGE_MASK; i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); @@ -237,7 +239,7 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the supplied size is only used by tlb_flush_page. */ void tlb_set_page(CPUArchState *env, target_ulong vaddr, - target_phys_addr_t paddr, int prot, + hwaddr paddr, int prot, int mmu_idx, target_ulong size) { MemoryRegionSection *section; @@ -246,13 +248,13 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, target_ulong code_address; uintptr_t addend; CPUTLBEntry *te; - target_phys_addr_t iotlb; + hwaddr iotlb; assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { tlb_add_large_page(env, vaddr, size); } - section = phys_page_find(paddr >> TARGET_PAGE_BITS); + section = phys_page_find(address_space_memory.dispatch, paddr >> TARGET_PAGE_BITS); #if defined(DEBUG_TLB) printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx " prot=%x idx=%d pd=0x%08lx\n", @@ -312,7 +314,9 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr, /* NOTE: this function can trigger an exception */ /* NOTE2: the returned address is not exactly the physical address: it - is the offset relative to phys_ram_base */ + * is actually a ram_addr_t (in system mode; the user mode emulation + * version of this function returns a guest virtual address). + */ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) { int mmu_idx, page_index, pd; @@ -323,11 +327,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) mmu_idx = cpu_mmu_index(env1); if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code != (addr & TARGET_PAGE_MASK))) { -#ifdef CONFIG_TCG_PASS_AREG0 cpu_ldub_code(env1, addr); -#else - ldub_code(addr); -#endif } pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK; mr = iotlb_to_region(pd); @@ -346,19 +346,18 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) #define MMUSUFFIX _cmmu #undef GETPC #define GETPC() ((uintptr_t)0) -#define env cpu_single_env #define SOFTMMU_CODE_ACCESS #define SHIFT 0 -#include "softmmu_template.h" +#include "exec/softmmu_template.h" #define SHIFT 1 -#include "softmmu_template.h" +#include "exec/softmmu_template.h" #define SHIFT 2 -#include "softmmu_template.h" +#include "exec/softmmu_template.h" #define SHIFT 3 -#include "softmmu_template.h" +#include "exec/softmmu_template.h" #undef env