X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=hw%2Fpci-host%2Fpnv_phb4.c;h=3c4c2dace0a33fbd20a1fd86abdf0bfe30786e85;hb=0f9668e0c197ab6de95f61a906703a1d127c11f8;hp=a7b638831ea5bbb7feac5d0189183e0034baaa76;hpb=f83460bb203a49dd1693bf8b664d2a935a5be621;p=mirror_qemu.git diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index a7b638831e..3c4c2dace0 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -10,7 +10,6 @@ #include "qemu/log.h" #include "qapi/visitor.h" #include "qapi/error.h" -#include "qemu-common.h" #include "monitor/monitor.h" #include "target/ppc/cpu.h" #include "hw/pci-host/pnv_phb4_regs.h" @@ -22,7 +21,6 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "qom/object.h" -#include "sysemu/sysemu.h" #include "trace.h" #define phb_error(phb, fmt, ...) \ @@ -228,16 +226,16 @@ static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index) /* TODO: Figure out how to implemet/decode AOMASK */ /* Check if it matches an enabled MMIO region in the PEC stack */ - if (memory_region_is_mapped(&phb->stack->mmbar0) && - base >= phb->stack->mmio0_base && - (base + size) <= (phb->stack->mmio0_base + phb->stack->mmio0_size)) { - parent = &phb->stack->mmbar0; - base -= phb->stack->mmio0_base; - } else if (memory_region_is_mapped(&phb->stack->mmbar1) && - base >= phb->stack->mmio1_base && - (base + size) <= (phb->stack->mmio1_base + phb->stack->mmio1_size)) { - parent = &phb->stack->mmbar1; - base -= phb->stack->mmio1_base; + if (memory_region_is_mapped(&phb->mmbar0) && + base >= phb->mmio0_base && + (base + size) <= (phb->mmio0_base + phb->mmio0_size)) { + parent = &phb->mmbar0; + base -= phb->mmio0_base; + } else if (memory_region_is_mapped(&phb->mmbar1) && + base >= phb->mmio1_base && + (base + size) <= (phb->mmio1_base + phb->mmio1_size)) { + parent = &phb->mmbar1; + base -= phb->mmio1_base; } else { phb_error(phb, "PHB MBAR %d out of parent bounds", index); return; @@ -486,6 +484,15 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb) flags = 0; } + /* + * When the PQ disable configuration bit is set, the check on the + * PQ state bits is disabled on the PHB side (for MSI only) and it + * is performed on the IC side instead. + */ + if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PQ_DISABLE) { + flags |= XIVE_SRC_PQ_DISABLE; + } + phb->xsrc.esb_shift = shift; phb->xsrc.esb_flags = flags; @@ -673,7 +680,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) switch (off) { case PHB_VERSION: - return phb->version; + return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version; /* Read-only */ case PHB_PHB4_GEN_CAP: @@ -861,44 +868,65 @@ const MemoryRegionOps pnv_phb4_xscom_ops = { static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, unsigned size) { - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); + PnvPHB4 *phb = PNV_PHB4(opaque); uint32_t reg = addr >> 3; /* TODO: add list of allowed registers and error out if not */ - return stack->nest_regs[reg]; + return phb->nest_regs[reg]; } -static void pnv_phb4_update_regions(PnvPhb4PecStack *stack) +/* + * Return the 'stack_no' of a PHB4. 'stack_no' is the order + * the PHB4 occupies in the PEC. This is the reverse of what + * pnv_phb4_pec_get_phb_id() does. + * + * E.g. a phb with phb_id = 4 and pec->index = 1 (PEC1) will + * be the second phb (stack_no = 1) of the PEC. + */ +static int pnv_phb4_get_phb_stack_no(PnvPHB4 *phb) { - PnvPHB4 *phb = stack->phb; + PnvPhb4PecState *pec = phb->pec; + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + int index = pec->index; + int stack_no = phb->phb_id; + + while (index--) { + stack_no -= pecc->num_phbs[index]; + } + + return stack_no; +} +static void pnv_phb4_update_regions(PnvPHB4 *phb) +{ /* Unmap first always */ if (memory_region_is_mapped(&phb->mr_regs)) { - memory_region_del_subregion(&stack->phbbar, &phb->mr_regs); + memory_region_del_subregion(&phb->phbbar, &phb->mr_regs); } if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { - memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio); + memory_region_del_subregion(&phb->intbar, &phb->xsrc.esb_mmio); } /* Map registers if enabled */ - if (memory_region_is_mapped(&stack->phbbar)) { - memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs); + if (memory_region_is_mapped(&phb->phbbar)) { + memory_region_add_subregion(&phb->phbbar, 0, &phb->mr_regs); } /* Map ESB if enabled */ - if (memory_region_is_mapped(&stack->intbar)) { - memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio); + if (memory_region_is_mapped(&phb->intbar)) { + memory_region_add_subregion(&phb->intbar, 0, &phb->xsrc.esb_mmio); } /* Check/update m32 */ pnv_phb4_check_all_mbt(phb); } -static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) +static void pnv_pec_phb_update_map(PnvPHB4 *phb) { - PnvPhb4PecState *pec = stack->pec; + PnvPhb4PecState *pec = phb->pec; MemoryRegion *sysmem = get_system_memory(); - uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN]; + uint64_t bar_en = phb->nest_regs[PEC_NEST_STK_BAR_EN]; + int stack_no = pnv_phb4_get_phb_stack_no(phb); uint64_t bar, mask, size; char name[64]; @@ -911,106 +939,106 @@ static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) */ /* Handle unmaps */ - if (memory_region_is_mapped(&stack->mmbar0) && + if (memory_region_is_mapped(&phb->mmbar0) && !(bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { - memory_region_del_subregion(sysmem, &stack->mmbar0); + memory_region_del_subregion(sysmem, &phb->mmbar0); } - if (memory_region_is_mapped(&stack->mmbar1) && + if (memory_region_is_mapped(&phb->mmbar1) && !(bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { - memory_region_del_subregion(sysmem, &stack->mmbar1); + memory_region_del_subregion(sysmem, &phb->mmbar1); } - if (memory_region_is_mapped(&stack->phbbar) && + if (memory_region_is_mapped(&phb->phbbar) && !(bar_en & PEC_NEST_STK_BAR_EN_PHB)) { - memory_region_del_subregion(sysmem, &stack->phbbar); + memory_region_del_subregion(sysmem, &phb->phbbar); } - if (memory_region_is_mapped(&stack->intbar) && + if (memory_region_is_mapped(&phb->intbar) && !(bar_en & PEC_NEST_STK_BAR_EN_INT)) { - memory_region_del_subregion(sysmem, &stack->intbar); + memory_region_del_subregion(sysmem, &phb->intbar); } /* Update PHB */ - pnv_phb4_update_regions(stack); + pnv_phb4_update_regions(phb); /* Handle maps */ - if (!memory_region_is_mapped(&stack->mmbar0) && + if (!memory_region_is_mapped(&phb->mmbar0) && (bar_en & PEC_NEST_STK_BAR_EN_MMIO0)) { - bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; - mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; + bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; + mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; size = ((~mask) >> 8) + 1; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio0", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->mmbar0, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->mmbar0); - stack->mmio0_base = bar; - stack->mmio0_size = size; - } - if (!memory_region_is_mapped(&stack->mmbar1) && + snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio0", + pec->chip_id, pec->index, stack_no); + memory_region_init(&phb->mmbar0, OBJECT(phb), name, size); + memory_region_add_subregion(sysmem, bar, &phb->mmbar0); + phb->mmio0_base = bar; + phb->mmio0_size = size; + } + if (!memory_region_is_mapped(&phb->mmbar1) && (bar_en & PEC_NEST_STK_BAR_EN_MMIO1)) { - bar = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; - mask = stack->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; + bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; + mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; size = ((~mask) >> 8) + 1; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-mmio1", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->mmbar1, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->mmbar1); - stack->mmio1_base = bar; - stack->mmio1_size = size; - } - if (!memory_region_is_mapped(&stack->phbbar) && + snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-mmio1", + pec->chip_id, pec->index, stack_no); + memory_region_init(&phb->mmbar1, OBJECT(phb), name, size); + memory_region_add_subregion(sysmem, bar, &phb->mmbar1); + phb->mmio1_base = bar; + phb->mmio1_size = size; + } + if (!memory_region_is_mapped(&phb->phbbar) && (bar_en & PEC_NEST_STK_BAR_EN_PHB)) { - bar = stack->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; + bar = phb->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; size = PNV_PHB4_NUM_REGS << 3; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-phb", - pec->chip_id, pec->index, stack->stack_no); - memory_region_init(&stack->phbbar, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->phbbar); + snprintf(name, sizeof(name), "pec-%d.%d-phb-%d", + pec->chip_id, pec->index, stack_no); + memory_region_init(&phb->phbbar, OBJECT(phb), name, size); + memory_region_add_subregion(sysmem, bar, &phb->phbbar); } - if (!memory_region_is_mapped(&stack->intbar) && + if (!memory_region_is_mapped(&phb->intbar) && (bar_en & PEC_NEST_STK_BAR_EN_INT)) { - bar = stack->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; + bar = phb->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; size = PNV_PHB4_MAX_INTs << 16; - snprintf(name, sizeof(name), "pec-%d.%d-stack-%d-int", - stack->pec->chip_id, stack->pec->index, stack->stack_no); - memory_region_init(&stack->intbar, OBJECT(stack), name, size); - memory_region_add_subregion(sysmem, bar, &stack->intbar); + snprintf(name, sizeof(name), "pec-%d.%d-phb-%d-int", + phb->pec->chip_id, phb->pec->index, stack_no); + memory_region_init(&phb->intbar, OBJECT(phb), name, size); + memory_region_add_subregion(sysmem, bar, &phb->intbar); } /* Update PHB */ - pnv_phb4_update_regions(stack); + pnv_phb4_update_regions(phb); } static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); - PnvPhb4PecState *pec = stack->pec; + PnvPHB4 *phb = PNV_PHB4(opaque); + PnvPhb4PecState *pec = phb->pec; uint32_t reg = addr >> 3; switch (reg) { case PEC_NEST_STK_PCI_NEST_FIR: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val; + phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val; break; case PEC_NEST_STK_PCI_NEST_FIR_CLR: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val; + phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val; break; case PEC_NEST_STK_PCI_NEST_FIR_SET: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val; + phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] |= val; break; case PEC_NEST_STK_PCI_NEST_FIR_MSK: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val; + phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] = val; break; case PEC_NEST_STK_PCI_NEST_FIR_MSKC: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val; + phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] &= val; break; case PEC_NEST_STK_PCI_NEST_FIR_MSKS: - stack->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val; + phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR_MSK] |= val; break; case PEC_NEST_STK_PCI_NEST_FIR_ACT0: case PEC_NEST_STK_PCI_NEST_FIR_ACT1: - stack->nest_regs[reg] = val; + phb->nest_regs[reg] = val; break; case PEC_NEST_STK_PCI_NEST_FIR_WOF: - stack->nest_regs[reg] = 0; + phb->nest_regs[reg] = 0; break; case PEC_NEST_STK_ERR_REPORT_0: case PEC_NEST_STK_ERR_REPORT_1: @@ -1018,39 +1046,39 @@ static void pnv_pec_stk_nest_xscom_write(void *opaque, hwaddr addr, /* Flag error ? */ break; case PEC_NEST_STK_PBCQ_MODE: - stack->nest_regs[reg] = val & 0xff00000000000000ull; + phb->nest_regs[reg] = val & 0xff00000000000000ull; break; case PEC_NEST_STK_MMIO_BAR0: case PEC_NEST_STK_MMIO_BAR0_MASK: case PEC_NEST_STK_MMIO_BAR1: case PEC_NEST_STK_MMIO_BAR1_MASK: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & + if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & (PEC_NEST_STK_BAR_EN_MMIO0 | PEC_NEST_STK_BAR_EN_MMIO1)) { phb_pec_error(pec, "Changing enabled BAR unsupported\n"); } - stack->nest_regs[reg] = val & 0xffffffffff000000ull; + phb->nest_regs[reg] = val & 0xffffffffff000000ull; break; case PEC_NEST_STK_PHB_REGS_BAR: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) { + if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_PHB) { phb_pec_error(pec, "Changing enabled BAR unsupported\n"); } - stack->nest_regs[reg] = val & 0xffffffffffc00000ull; + phb->nest_regs[reg] = val & 0xffffffffffc00000ull; break; case PEC_NEST_STK_INT_BAR: - if (stack->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) { + if (phb->nest_regs[PEC_NEST_STK_BAR_EN] & PEC_NEST_STK_BAR_EN_INT) { phb_pec_error(pec, "Changing enabled BAR unsupported\n"); } - stack->nest_regs[reg] = val & 0xfffffff000000000ull; + phb->nest_regs[reg] = val & 0xfffffff000000000ull; break; case PEC_NEST_STK_BAR_EN: - stack->nest_regs[reg] = val & 0xf000000000000000ull; - pnv_pec_stk_update_map(stack); + phb->nest_regs[reg] = val & 0xf000000000000000ull; + pnv_pec_phb_update_map(phb); break; case PEC_NEST_STK_DATA_FRZ_TYPE: case PEC_NEST_STK_PBCQ_TUN_BAR: /* Not used for now */ - stack->nest_regs[reg] = val; + phb->nest_regs[reg] = val; break; default: qemu_log_mask(LOG_UNIMP, "phb4_pec: nest_xscom_write 0x%"HWADDR_PRIx @@ -1071,54 +1099,54 @@ static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = { static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr, unsigned size) { - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); + PnvPHB4 *phb = PNV_PHB4(opaque); uint32_t reg = addr >> 3; /* TODO: add list of allowed registers and error out if not */ - return stack->pci_regs[reg]; + return phb->pci_regs[reg]; } static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(opaque); + PnvPHB4 *phb = PNV_PHB4(opaque); uint32_t reg = addr >> 3; switch (reg) { case PEC_PCI_STK_PCI_FIR: - stack->pci_regs[reg] = val; + phb->pci_regs[reg] = val; break; case PEC_PCI_STK_PCI_FIR_CLR: - stack->pci_regs[PEC_PCI_STK_PCI_FIR] &= val; + phb->pci_regs[PEC_PCI_STK_PCI_FIR] &= val; break; case PEC_PCI_STK_PCI_FIR_SET: - stack->pci_regs[PEC_PCI_STK_PCI_FIR] |= val; + phb->pci_regs[PEC_PCI_STK_PCI_FIR] |= val; break; case PEC_PCI_STK_PCI_FIR_MSK: - stack->pci_regs[reg] = val; + phb->pci_regs[reg] = val; break; case PEC_PCI_STK_PCI_FIR_MSKC: - stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val; + phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val; break; case PEC_PCI_STK_PCI_FIR_MSKS: - stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val; + phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val; break; case PEC_PCI_STK_PCI_FIR_ACT0: case PEC_PCI_STK_PCI_FIR_ACT1: - stack->pci_regs[reg] = val; + phb->pci_regs[reg] = val; break; case PEC_PCI_STK_PCI_FIR_WOF: - stack->pci_regs[reg] = 0; + phb->pci_regs[reg] = 0; break; case PEC_PCI_STK_ETU_RESET: - stack->pci_regs[reg] = val & 0x8000000000000000ull; + phb->pci_regs[reg] = val & 0x8000000000000000ull; /* TODO: Implement reset */ break; case PEC_PCI_STK_PBAIB_ERR_REPORT: break; case PEC_PCI_STK_PBAIB_TX_CMD_CRED: case PEC_PCI_STK_PBAIB_TX_DAT_CRED: - stack->pci_regs[reg] = val; + phb->pci_regs[reg] = val; break; default: qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx @@ -1247,7 +1275,9 @@ static void pnv_phb4_translate_tve(PnvPhb4DMASpace *ds, hwaddr addr, /* TODO: Limit to support IO page sizes */ /* TODO: Multi-level untested */ - while ((lev--) >= 0) { + do { + lev--; + /* Grab the TCE address */ taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3); if (dma_memory_read(&address_space_memory, taddr, &tce, @@ -1268,21 +1298,22 @@ static void pnv_phb4_translate_tve(PnvPhb4DMASpace *ds, hwaddr addr, } sh -= tbl_shift; base = tce & ~0xfffull; - } + } while (lev >= 0); /* We exit the loop with TCE being the final TCE */ - tce_mask = ~((1ull << tce_shift) - 1); - tlb->iova = addr & tce_mask; - tlb->translated_addr = tce & tce_mask; - tlb->addr_mask = ~tce_mask; - tlb->perm = tce & 3; if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr); phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, is_write ? 'W' : 'R', tve); phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", tta, lev, tts, tps); + return; } + tce_mask = ~((1ull << tce_shift) - 1); + tlb->iova = addr & tce_mask; + tlb->translated_addr = tce & tce_mask; + tlb->addr_mask = ~tce_mask; + tlb->perm = tce & 3; } } @@ -1362,7 +1393,7 @@ int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index) int offset = 0; while (index--) { - offset += pecc->num_stacks[index]; + offset += pecc->num_phbs[index]; } return offset + stack_index; @@ -1434,7 +1465,7 @@ static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn) ds = pnv_phb4_dma_find(phb, bus, devfn); if (ds == NULL) { - ds = g_malloc0(sizeof(PnvPhb4DMASpace)); + ds = g_new0(PnvPhb4DMASpace, 1); ds->bus = bus; ds->devfn = devfn; ds->pe_num = PHB_INVALID_PE; @@ -1459,9 +1490,9 @@ static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn) static void pnv_phb4_xscom_realize(PnvPHB4 *phb) { - PnvPhb4PecStack *stack = phb->stack; - PnvPhb4PecState *pec = stack->pec; + PnvPhb4PecState *pec = phb->pec; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + int stack_no = pnv_phb4_get_phb_stack_no(phb); uint32_t pec_nest_base; uint32_t pec_pci_base; char name[64]; @@ -1469,22 +1500,22 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb) assert(pec); /* Initialize the XSCOM regions for the stack registers */ - snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-stack-%d", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->nest_regs_mr, OBJECT(stack), - &pnv_pec_stk_nest_xscom_ops, stack, name, + snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest-phb-%d", + pec->chip_id, pec->index, stack_no); + pnv_xscom_region_init(&phb->nest_regs_mr, OBJECT(phb), + &pnv_pec_stk_nest_xscom_ops, phb, name, PHB4_PEC_NEST_STK_REGS_COUNT); - snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(stack), - &pnv_pec_stk_pci_xscom_ops, stack, name, + snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d", + pec->chip_id, pec->index, stack_no); + pnv_xscom_region_init(&phb->pci_regs_mr, OBJECT(phb), + &pnv_pec_stk_pci_xscom_ops, phb, name, PHB4_PEC_PCI_STK_REGS_COUNT); /* PHB pass-through */ - snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-stack-%d-phb", - pec->chip_id, pec->index, stack->stack_no); - pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(phb), + snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d", + pec->chip_id, pec->index, stack_no); + pnv_xscom_region_init(&phb->phb_regs_mr, OBJECT(phb), &pnv_phb4_xscom_ops, phb, name, 0x40); pec_nest_base = pecc->xscom_nest_base(pec); @@ -1492,15 +1523,15 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb) /* Populate the XSCOM address space. */ pnv_xscom_add_subregion(pec->chip, - pec_nest_base + 0x40 * (stack->stack_no + 1), - &stack->nest_regs_mr); + pec_nest_base + 0x40 * (stack_no + 1), + &phb->nest_regs_mr); pnv_xscom_add_subregion(pec->chip, - pec_pci_base + 0x40 * (stack->stack_no + 1), - &stack->pci_regs_mr); + pec_pci_base + 0x40 * (stack_no + 1), + &phb->pci_regs_mr); pnv_xscom_add_subregion(pec->chip, pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + - 0x40 * stack->stack_no, - &stack->phb_regs_mr); + 0x40 * stack_no, + &phb->phb_regs_mr); } static void pnv_phb4_instance_init(Object *obj) @@ -1513,86 +1544,14 @@ static void pnv_phb4_instance_init(Object *obj) object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); } -static PnvPhb4PecStack *pnv_phb4_get_stack(PnvChip *chip, PnvPHB4 *phb, - Error **errp) -{ - Pnv9Chip *chip9 = PNV9_CHIP(chip); - int chip_id = phb->chip_id; - int index = phb->phb_id; - int i, j; - - for (i = 0; i < chip->num_pecs; i++) { - /* - * For each PEC, check the amount of stacks it supports - * and see if the given phb4 index matches a stack. - */ - PnvPhb4PecState *pec = &chip9->pecs[i]; - - for (j = 0; j < pec->num_stacks; j++) { - if (index == pnv_phb4_pec_get_phb_id(pec, j)) { - return &pec->stacks[j]; - } - } - } - - error_setg(errp, - "pnv-phb4 chip-id %d index %d didn't match any existing PEC", - chip_id, index); - - return NULL; -} - static void pnv_phb4_realize(DeviceState *dev, Error **errp) { PnvPHB4 *phb = PNV_PHB4(dev); PCIHostState *pci = PCI_HOST_BRIDGE(dev); XiveSource *xsrc = &phb->xsrc; - Error *local_err = NULL; int nr_irqs; char name[32]; - /* User created PHB */ - if (!phb->stack) { - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); - PnvPhb4PecClass *pecc; - BusState *s; - - if (!chip) { - error_setg(errp, "invalid chip id: %d", phb->chip_id); - return; - } - - phb->stack = pnv_phb4_get_stack(chip, phb, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - /* All other phb properties but 'version' are already set */ - pecc = PNV_PHB4_PEC_GET_CLASS(phb->stack->pec); - object_property_set_int(OBJECT(phb), "version", pecc->version, - &error_fatal); - - /* - * Assign stack->phb since pnv_phb4_update_regions() uses it - * to access the phb. - */ - phb->stack->phb = phb; - - /* - * Reparent user created devices to the chip to build - * correctly the device tree. - */ - pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id); - - s = qdev_get_parent_bus(DEVICE(chip)); - if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) { - error_propagate(errp, local_err); - return; - } - } - /* Set the "big_phb" flag */ phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3; @@ -1624,12 +1583,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb); pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; - /* Add a single Root port if running with defaults */ - if (defaults_enabled()) { - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), - TYPE_PNV_PHB4_ROOT_PORT); - } - /* Setup XIVE Source */ if (phb->big_phb) { nr_irqs = PNV_PHB4_MAX_INTs; @@ -1659,15 +1612,64 @@ static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, return phb->bus_path; } -static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno) +/* + * Address base trigger mode (POWER10) + * + * Trigger directly the IC ESB page + */ +static void pnv_phb4_xive_notify_abt(PnvPHB4 *phb, uint32_t srcno, + bool pq_checked) +{ + uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; + uint64_t data = 0; /* trigger data : don't care */ + hwaddr addr; + MemTxResult result; + int esb_shift; + + if (notif_port & PHB_INT_NOTIFY_ADDR_64K) { + esb_shift = 16; + } else { + esb_shift = 12; + } + + /* Compute the address of the IC ESB management page */ + addr = (notif_port & ~PHB_INT_NOTIFY_ADDR_64K); + addr |= (1ull << (esb_shift + 1)) * srcno; + addr |= (1ull << esb_shift); + + /* + * When the PQ state bits are checked on the PHB, the associated + * PQ state bits on the IC should be ignored. Use the unconditional + * trigger offset to inject a trigger on the IC. This is always + * the case for LSIs + */ + if (pq_checked) { + addr |= XIVE_ESB_INJECT; + } + + trace_pnv_phb4_xive_notify_ic(addr, data); + + address_space_stq_be(&address_space_memory, addr, data, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", addr); + return; + } +} + +static void pnv_phb4_xive_notify_ic(PnvPHB4 *phb, uint32_t srcno, + bool pq_checked) { - PnvPHB4 *phb = PNV_PHB4(xf); uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; - uint64_t data = XIVE_TRIGGER_PQ | offset | srcno; + uint64_t data = offset | srcno; MemTxResult result; - trace_pnv_phb4_xive_notify(notif_port, data); + if (pq_checked) { + data |= XIVE_TRIGGER_PQ; + } + + trace_pnv_phb4_xive_notify_ic(notif_port, data); address_space_stq_be(&address_space_memory, notif_port, data, MEMTXATTRS_UNSPECIFIED, &result); @@ -1677,12 +1679,23 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno) } } +static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno, + bool pq_checked) +{ + PnvPHB4 *phb = PNV_PHB4(xf); + + if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE) { + pnv_phb4_xive_notify_abt(phb, srcno, pq_checked); + } else { + pnv_phb4_xive_notify_ic(phb, srcno, pq_checked); + } +} + static Property pnv_phb4_properties[] = { DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0), DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0), - DEFINE_PROP_UINT64("version", PnvPHB4, version, 0), - DEFINE_PROP_LINK("stack", PnvPHB4, stack, TYPE_PNV_PHB4_PEC_STACK, - PnvPhb4PecStack *), + DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC, + PnvPhb4PecState *), DEFINE_PROP_END_OF_LIST(), }; @@ -1696,7 +1709,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data) dc->realize = pnv_phb4_realize; device_class_set_props(dc, pnv_phb4_properties); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->user_creatable = true; + dc->user_creatable = false; xfc->notify = pnv_phb4_xive_notify; } @@ -1713,6 +1726,12 @@ static const TypeInfo pnv_phb4_type_info = { } }; +static const TypeInfo pnv_phb5_type_info = { + .name = TYPE_PNV_PHB5, + .parent = TYPE_PNV_PHB4, + .instance_size = sizeof(PnvPHB4), +}; + static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data) { BusClass *k = BUS_CLASS(klass); @@ -1788,7 +1807,7 @@ static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data) PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); dc->desc = "IBM PHB4 PCIE Root Port"; - dc->user_creatable = true; + dc->user_creatable = false; device_class_set_parent_realize(dc, pnv_phb4_root_port_realize, &rpc->parent_realize); @@ -1812,11 +1831,32 @@ static const TypeInfo pnv_phb4_root_port_info = { .class_init = pnv_phb4_root_port_class_init, }; +static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + dc->desc = "IBM PHB5 PCIE Root Port"; + dc->user_creatable = false; + + k->vendor_id = PCI_VENDOR_ID_IBM; + k->device_id = PNV_PHB5_DEVICE_ID; +} + +static const TypeInfo pnv_phb5_root_port_info = { + .name = TYPE_PNV_PHB5_ROOT_PORT, + .parent = TYPE_PNV_PHB4_ROOT_PORT, + .instance_size = sizeof(PnvPHB4RootPort), + .class_init = pnv_phb5_root_port_class_init, +}; + static void pnv_phb4_register_types(void) { type_register_static(&pnv_phb4_root_bus_info); + type_register_static(&pnv_phb5_root_port_info); type_register_static(&pnv_phb4_root_port_info); type_register_static(&pnv_phb4_type_info); + type_register_static(&pnv_phb5_type_info); type_register_static(&pnv_phb4_iommu_memory_region_info); } @@ -1824,10 +1864,15 @@ type_init(pnv_phb4_register_types); void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon) { + uint64_t notif_port = + phb->regs[PHB_INT_NOTIFY_ADDR >> 3] & ~PHB_INT_NOTIFY_ADDR_64K; uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; + bool abt = !!(phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE); - monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x\n", + monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x %s @%"HWADDR_PRIx"\n", phb->chip_id, phb->phb_id, - offset, offset + phb->xsrc.nr_irqs - 1); + offset, offset + phb->xsrc.nr_irqs - 1, + abt ? "ABT" : "", + notif_port); xive_source_pic_print_info(&phb->xsrc, 0, mon); }