X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=hw%2Fppc405_uc.c;h=a6e74318829ad85a9cbdf21167b3b5c583c93e2c;hb=dd7b25b5b47df8aaf5580faaf3f60b2a1b779c37;hp=334187e53b4fb09b9a637e7a858254acdfb5d5e9;hpb=9e8a69cfd6f0fe2585528fc7a85110fc25c05d0b;p=qemu.git diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 334187e53..a6e743188 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -28,6 +28,7 @@ #include "qemu-timer.h" #include "sysemu.h" #include "qemu-log.h" +#include "exec-memory.h" #define DEBUG_OPBA #define DEBUG_SDRAM @@ -51,39 +52,42 @@ ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); else bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); - stl_phys(bdloc + 0x00, bd->bi_memstart); - stl_phys(bdloc + 0x04, bd->bi_memsize); - stl_phys(bdloc + 0x08, bd->bi_flashstart); - stl_phys(bdloc + 0x0C, bd->bi_flashsize); - stl_phys(bdloc + 0x10, bd->bi_flashoffset); - stl_phys(bdloc + 0x14, bd->bi_sramstart); - stl_phys(bdloc + 0x18, bd->bi_sramsize); - stl_phys(bdloc + 0x1C, bd->bi_bootflags); - stl_phys(bdloc + 0x20, bd->bi_ipaddr); - for (i = 0; i < 6; i++) + stl_be_phys(bdloc + 0x00, bd->bi_memstart); + stl_be_phys(bdloc + 0x04, bd->bi_memsize); + stl_be_phys(bdloc + 0x08, bd->bi_flashstart); + stl_be_phys(bdloc + 0x0C, bd->bi_flashsize); + stl_be_phys(bdloc + 0x10, bd->bi_flashoffset); + stl_be_phys(bdloc + 0x14, bd->bi_sramstart); + stl_be_phys(bdloc + 0x18, bd->bi_sramsize); + stl_be_phys(bdloc + 0x1C, bd->bi_bootflags); + stl_be_phys(bdloc + 0x20, bd->bi_ipaddr); + for (i = 0; i < 6; i++) { stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]); - stw_phys(bdloc + 0x2A, bd->bi_ethspeed); - stl_phys(bdloc + 0x2C, bd->bi_intfreq); - stl_phys(bdloc + 0x30, bd->bi_busfreq); - stl_phys(bdloc + 0x34, bd->bi_baudrate); - for (i = 0; i < 4; i++) + } + stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed); + stl_be_phys(bdloc + 0x2C, bd->bi_intfreq); + stl_be_phys(bdloc + 0x30, bd->bi_busfreq); + stl_be_phys(bdloc + 0x34, bd->bi_baudrate); + for (i = 0; i < 4; i++) { stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]); + } for (i = 0; i < 32; i++) { stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]); } - stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq); - stl_phys(bdloc + 0x60, bd->bi_pci_busfreq); - for (i = 0; i < 6; i++) + stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq); + stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq); + for (i = 0; i < 6; i++) { stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); + } n = 0x6A; if (flags & 0x00000001) { for (i = 0; i < 6; i++) stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]); } - stl_phys(bdloc + n, bd->bi_opbfreq); + stl_be_phys(bdloc + n, bd->bi_opbfreq); n += 4; for (i = 0; i < 2; i++) { - stl_phys(bdloc + n, bd->bi_iic_fast[i]); + stl_be_phys(bdloc + n, bd->bi_iic_fast[i]); n += 4; } @@ -169,7 +173,7 @@ static void ppc4xx_plb_init(CPUState *env) { ppc4xx_plb_t *plb; - plb = qemu_mallocz(sizeof(ppc4xx_plb_t)); + plb = g_malloc0(sizeof(ppc4xx_plb_t)); ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); @@ -245,7 +249,7 @@ static void ppc4xx_pob_init(CPUState *env) { ppc4xx_pob_t *pob; - pob = qemu_mallocz(sizeof(ppc4xx_pob_t)); + pob = g_malloc0(sizeof(ppc4xx_pob_t)); ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); @@ -256,6 +260,7 @@ static void ppc4xx_pob_init(CPUState *env) /* OPB arbitrer */ typedef struct ppc4xx_opba_t ppc4xx_opba_t; struct ppc4xx_opba_t { + MemoryRegion io; uint8_t cr; uint8_t pr; }; @@ -354,16 +359,12 @@ static void opba_writel (void *opaque, opba_writeb(opaque, addr + 1, value >> 16); } -static CPUReadMemoryFunc * const opba_read[] = { - &opba_readb, - &opba_readw, - &opba_readl, -}; - -static CPUWriteMemoryFunc * const opba_write[] = { - &opba_writeb, - &opba_writew, - &opba_writel, +static const MemoryRegionOps opba_ops = { + .old_mmio = { + .read = { opba_readb, opba_readw, opba_readl, }, + .write = { opba_writeb, opba_writew, opba_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ppc4xx_opba_reset (void *opaque) @@ -378,15 +379,13 @@ static void ppc4xx_opba_reset (void *opaque) static void ppc4xx_opba_init(target_phys_addr_t base) { ppc4xx_opba_t *opba; - int io; - opba = qemu_mallocz(sizeof(ppc4xx_opba_t)); + opba = g_malloc0(sizeof(ppc4xx_opba_t)); #ifdef DEBUG_OPBA printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(opba_read, opba_write, opba, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x002, io); + memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002); + memory_region_add_subregion(get_system_memory(), base, &opba->io); qemu_register_reset(ppc4xx_opba_reset, opba); } @@ -579,7 +578,7 @@ static void ppc405_ebc_init(CPUState *env) { ppc4xx_ebc_t *ebc; - ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t)); + ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); qemu_register_reset(&ebc_reset, ebc); ppc_dcr_register(env, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc); @@ -662,7 +661,7 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) { ppc405_dma_t *dma; - dma = qemu_mallocz(sizeof(ppc405_dma_t)); + dma = g_malloc0(sizeof(ppc405_dma_t)); memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); qemu_register_reset(&ppc405_dma_reset, dma); ppc_dcr_register(env, DMA0_CR0, @@ -719,6 +718,7 @@ static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4]) /* GPIO */ typedef struct ppc405_gpio_t ppc405_gpio_t; struct ppc405_gpio_t { + MemoryRegion io; uint32_t or; uint32_t tcr; uint32_t osrh; @@ -786,16 +786,12 @@ static void ppc405_gpio_writel (void *opaque, #endif } -static CPUReadMemoryFunc * const ppc405_gpio_read[] = { - &ppc405_gpio_readb, - &ppc405_gpio_readw, - &ppc405_gpio_readl, -}; - -static CPUWriteMemoryFunc * const ppc405_gpio_write[] = { - &ppc405_gpio_writeb, - &ppc405_gpio_writew, - &ppc405_gpio_writel, +static const MemoryRegionOps ppc405_gpio_ops = { + .old_mmio = { + .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, }, + .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ppc405_gpio_reset (void *opaque) @@ -805,15 +801,13 @@ static void ppc405_gpio_reset (void *opaque) static void ppc405_gpio_init(target_phys_addr_t base) { ppc405_gpio_t *gpio; - int io; - gpio = qemu_mallocz(sizeof(ppc405_gpio_t)); + gpio = g_malloc0(sizeof(ppc405_gpio_t)); #ifdef DEBUG_GPIO printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x038, io); + memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038); + memory_region_add_subregion(get_system_memory(), base, &gpio->io); qemu_register_reset(&ppc405_gpio_reset, gpio); } @@ -828,7 +822,9 @@ enum { typedef struct ppc405_ocm_t ppc405_ocm_t; struct ppc405_ocm_t { - target_ulong offset; + MemoryRegion ram; + MemoryRegion isarc_ram; + MemoryRegion dsarc_ram; uint32_t isarc; uint32_t isacntl; uint32_t dsarc; @@ -851,16 +847,15 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, if (ocm->isacntl & 0x80000000) { /* Unmap previously assigned memory region */ printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); - cpu_register_physical_memory(ocm->isarc, 0x04000000, - IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); } if (isacntl & 0x80000000) { /* Map new instruction memory region */ #ifdef DEBUG_OCM printf("OCM map ISA %08" PRIx32 "\n", isarc); #endif - cpu_register_physical_memory(isarc, 0x04000000, - ocm->offset | IO_MEM_RAM); + memory_region_add_subregion(get_system_memory(), isarc, + &ocm->isarc_ram); } } if (ocm->dsarc != dsarc || @@ -872,8 +867,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, #ifdef DEBUG_OCM printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); #endif - cpu_register_physical_memory(ocm->dsarc, 0x04000000, - IO_MEM_UNASSIGNED); + memory_region_del_subregion(get_system_memory(), + &ocm->dsarc_ram); } } if (dsacntl & 0x80000000) { @@ -883,8 +878,8 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, #ifdef DEBUG_OCM printf("OCM map DSA %08" PRIx32 "\n", dsarc); #endif - cpu_register_physical_memory(dsarc, 0x04000000, - ocm->offset | IO_MEM_RAM); + memory_region_add_subregion(get_system_memory(), dsarc, + &ocm->dsarc_ram); } } } @@ -969,8 +964,11 @@ static void ppc405_ocm_init(CPUState *env) { ppc405_ocm_t *ocm; - ocm = qemu_mallocz(sizeof(ppc405_ocm_t)); - ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096); + ocm = g_malloc0(sizeof(ppc405_ocm_t)); + /* XXX: Size is 4096 or 0x04000000 */ + memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096); + memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram, + 0, 4096); qemu_register_reset(&ocm_reset, ocm); ppc_dcr_register(env, OCM0_ISARC, ocm, &dcr_read_ocm, &dcr_write_ocm); @@ -987,6 +985,7 @@ static void ppc405_ocm_init(CPUState *env) typedef struct ppc4xx_i2c_t ppc4xx_i2c_t; struct ppc4xx_i2c_t { qemu_irq irq; + MemoryRegion iomem; uint8_t mdata; uint8_t lmadr; uint8_t hmadr; @@ -1183,16 +1182,12 @@ static void ppc4xx_i2c_writel (void *opaque, ppc4xx_i2c_writeb(opaque, addr + 3, value); } -static CPUReadMemoryFunc * const i2c_read[] = { - &ppc4xx_i2c_readb, - &ppc4xx_i2c_readw, - &ppc4xx_i2c_readl, -}; - -static CPUWriteMemoryFunc * const i2c_write[] = { - &ppc4xx_i2c_writeb, - &ppc4xx_i2c_writew, - &ppc4xx_i2c_writel, +static const MemoryRegionOps i2c_ops = { + .old_mmio = { + .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, }, + .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ppc4xx_i2c_reset (void *opaque) @@ -1214,16 +1209,14 @@ static void ppc4xx_i2c_reset (void *opaque) static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) { ppc4xx_i2c_t *i2c; - int io; - i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t)); + i2c = g_malloc0(sizeof(ppc4xx_i2c_t)); i2c->irq = irq; #ifdef DEBUG_I2C printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(i2c_read, i2c_write, i2c, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x011, io); + memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011); + memory_region_add_subregion(get_system_memory(), base, &i2c->iomem); qemu_register_reset(ppc4xx_i2c_reset, i2c); } @@ -1231,6 +1224,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq) /* General purpose timers */ typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; struct ppc4xx_gpt_t { + MemoryRegion iomem; int64_t tb_offset; uint32_t tb_freq; struct QEMUTimer *timer; @@ -1347,7 +1341,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr) switch (addr) { case 0x00: /* Time base counter */ - ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset, + ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset, gpt->tb_freq, get_ticks_per_sec()); break; case 0x10: @@ -1404,7 +1398,7 @@ static void ppc4xx_gpt_writel (void *opaque, case 0x00: /* Time base counter */ gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq) - - qemu_get_clock(vm_clock); + - qemu_get_clock_ns(vm_clock); ppc4xx_gpt_compute_timer(gpt); break; case 0x10: @@ -1451,16 +1445,12 @@ static void ppc4xx_gpt_writel (void *opaque, } } -static CPUReadMemoryFunc * const gpt_read[] = { - &ppc4xx_gpt_readb, - &ppc4xx_gpt_readw, - &ppc4xx_gpt_readl, -}; - -static CPUWriteMemoryFunc * const gpt_write[] = { - &ppc4xx_gpt_writeb, - &ppc4xx_gpt_writew, - &ppc4xx_gpt_writel, +static const MemoryRegionOps gpt_ops = { + .old_mmio = { + .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, }, + .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void ppc4xx_gpt_cb (void *opaque) @@ -1495,18 +1485,17 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5]) { ppc4xx_gpt_t *gpt; int i; - int io; - gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t)); + gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); for (i = 0; i < 5; i++) { gpt->irqs[i] = irqs[i]; } - gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt); + gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt); #ifdef DEBUG_GPT printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); #endif - io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x0d4, io); + memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4); + memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); qemu_register_reset(ppc4xx_gpt_reset, gpt); } @@ -1728,7 +1717,7 @@ static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) ppc40x_mal_t *mal; int i; - mal = qemu_mallocz(sizeof(ppc40x_mal_t)); + mal = g_malloc0(sizeof(ppc40x_mal_t)); for (i = 0; i < 4; i++) mal->irqs[i] = irqs[i]; qemu_register_reset(&ppc40x_mal_reset, mal); @@ -2093,7 +2082,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], { ppc405cr_cpc_t *cpc; - cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t)); + cpc = g_malloc0(sizeof(ppc405cr_cpc_t)); memcpy(cpc->clk_setup, clk_setup, PPC405CR_CLK_NB * sizeof(clk_setup_t)); cpc->sysclk = sysclk; @@ -2118,10 +2107,12 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], qemu_register_reset(ppc405cr_cpc_reset, cpc); } -CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], - target_phys_addr_t ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init) +CPUState *ppc405cr_init(MemoryRegion *address_space_mem, + MemoryRegion ram_memories[4], + target_phys_addr_t ram_bases[4], + target_phys_addr_t ram_sizes[4], + uint32_t sysclk, qemu_irq **picp, + int do_init) { clk_setup_t clk_setup[PPC405CR_CLK_NB]; qemu_irq dma_irqs[4]; @@ -2139,7 +2130,7 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], /* OBP arbitrer */ ppc4xx_opba_init(0xef600600); /* Universal interrupt controller */ - irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); + irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; irqs[PPCUIC_OUTPUT_CINT] = @@ -2147,7 +2138,8 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); *picp = pic; /* SDRAM controller */ - ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[14], 1, ram_memories, + ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ @@ -2158,12 +2150,14 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], ppc405_dma_init(env, dma_irqs); /* Serial ports */ if (serial_hds[0] != NULL) { - serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, - serial_hds[0], 1, 1); + serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + PPC_SERIAL_MM_BAUDBASE, serial_hds[0], + DEVICE_BIG_ENDIAN); } if (serial_hds[1] != NULL) { - serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, - serial_hds[1], 1, 1); + serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + PPC_SERIAL_MM_BAUDBASE, serial_hds[1], + DEVICE_BIG_ENDIAN); } /* IIC controller */ ppc405_i2c_init(0xef600500, pic[2]); @@ -2430,7 +2424,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], { ppc405ep_cpc_t *cpc; - cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t)); + cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); memcpy(cpc->clk_setup, clk_setup, PPC405EP_CLK_NB * sizeof(clk_setup_t)); cpc->jtagid = 0x20267049; @@ -2462,10 +2456,12 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], #endif } -CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], - target_phys_addr_t ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, - int do_init) +CPUState *ppc405ep_init(MemoryRegion *address_space_mem, + MemoryRegion ram_memories[2], + target_phys_addr_t ram_bases[2], + target_phys_addr_t ram_sizes[2], + uint32_t sysclk, qemu_irq **picp, + int do_init) { clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; @@ -2487,7 +2483,7 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], /* OBP arbitrer */ ppc4xx_opba_init(0xef600600); /* Universal interrupt controller */ - irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); + irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; irqs[PPCUIC_OUTPUT_CINT] = @@ -2496,7 +2492,8 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], *picp = pic; /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[17], 2, ram_memories, + ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ @@ -2511,12 +2508,14 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], ppc405_gpio_init(0xef600700); /* Serial ports */ if (serial_hds[0] != NULL) { - serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, - serial_hds[0], 1, 1); + serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + PPC_SERIAL_MM_BAUDBASE, serial_hds[0], + DEVICE_BIG_ENDIAN); } if (serial_hds[1] != NULL) { - serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, - serial_hds[1], 1, 1); + serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + PPC_SERIAL_MM_BAUDBASE, serial_hds[1], + DEVICE_BIG_ENDIAN); } /* OCM */ ppc405_ocm_init(env);