X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ioport.c;h=0d2611d14298f7747b8b71aaad5a0d184584aad8;hb=82b2b32a323bbb5824b4fbe63a3bca50f827e28e;hp=8f1ae452c6c1500e0a807754c61722734cfcdcc9;hpb=99a0949b720a0936da2052cb9a46db04ffc6db29;p=qemu.git diff --git a/ioport.c b/ioport.c index 8f1ae452c..0d2611d14 100644 --- a/ioport.c +++ b/ioport.c @@ -26,6 +26,7 @@ */ #include "ioport.h" +#include "trace.h" /***********************************************************/ /* IO Port */ @@ -136,7 +137,7 @@ static int ioport_bsize(int size, int *bsize) } /* size is the word size in byte */ -int register_ioport_read(a_pio_addr start, int length, int size, +int register_ioport_read(pio_addr_t start, int length, int size, IOPortReadFunc *func, void *opaque) { int i, bsize; @@ -148,14 +149,15 @@ int register_ioport_read(a_pio_addr start, int length, int size, for(i = start; i < start + length; i += size) { ioport_read_table[bsize][i] = func; if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque) - hw_error("register_ioport_read: invalid opaque"); + hw_error("register_ioport_read: invalid opaque for address 0x%x", + i); ioport_opaque[i] = opaque; } return 0; } /* size is the word size in byte */ -int register_ioport_write(a_pio_addr start, int length, int size, +int register_ioport_write(pio_addr_t start, int length, int size, IOPortWriteFunc *func, void *opaque) { int i, bsize; @@ -167,69 +169,147 @@ int register_ioport_write(a_pio_addr start, int length, int size, for(i = start; i < start + length; i += size) { ioport_write_table[bsize][i] = func; if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque) - hw_error("register_ioport_write: invalid opaque"); + hw_error("register_ioport_write: invalid opaque for address 0x%x", + i); ioport_opaque[i] = opaque; } return 0; } -void isa_unassign_ioport(a_pio_addr start, int length) +static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr) +{ + IORange *ioport = opaque; + uint64_t data; + + ioport->ops->read(ioport, addr - ioport->base, 1, &data); + return data; +} + +static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr) +{ + IORange *ioport = opaque; + uint64_t data; + + ioport->ops->read(ioport, addr - ioport->base, 2, &data); + return data; +} + +static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr) +{ + IORange *ioport = opaque; + uint64_t data; + + ioport->ops->read(ioport, addr - ioport->base, 4, &data); + return data; +} + +static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data) +{ + IORange *ioport = opaque; + + ioport->ops->write(ioport, addr - ioport->base, 1, data); +} + +static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data) +{ + IORange *ioport = opaque; + + ioport->ops->write(ioport, addr - ioport->base, 2, data); +} + +static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data) +{ + IORange *ioport = opaque; + + ioport->ops->write(ioport, addr - ioport->base, 4, data); +} + +void ioport_register(IORange *ioport) +{ + register_ioport_read(ioport->base, ioport->len, 1, + ioport_readb_thunk, ioport); + register_ioport_read(ioport->base, ioport->len, 2, + ioport_readw_thunk, ioport); + register_ioport_read(ioport->base, ioport->len, 4, + ioport_readl_thunk, ioport); + register_ioport_write(ioport->base, ioport->len, 1, + ioport_writeb_thunk, ioport); + register_ioport_write(ioport->base, ioport->len, 2, + ioport_writew_thunk, ioport); + register_ioport_write(ioport->base, ioport->len, 4, + ioport_writel_thunk, ioport); +} + +void isa_unassign_ioport(pio_addr_t start, int length) { int i; for(i = start; i < start + length; i++) { - ioport_read_table[0][i] = default_ioport_readb; - ioport_read_table[1][i] = default_ioport_readw; - ioport_read_table[2][i] = default_ioport_readl; + ioport_read_table[0][i] = NULL; + ioport_read_table[1][i] = NULL; + ioport_read_table[2][i] = NULL; - ioport_write_table[0][i] = default_ioport_writeb; - ioport_write_table[1][i] = default_ioport_writew; - ioport_write_table[2][i] = default_ioport_writel; + ioport_write_table[0][i] = NULL; + ioport_write_table[1][i] = NULL; + ioport_write_table[2][i] = NULL; ioport_opaque[i] = NULL; } } +bool isa_is_ioport_assigned(pio_addr_t start) +{ + return (ioport_read_table[0][start] || ioport_write_table[0][start] || + ioport_read_table[1][start] || ioport_write_table[1][start] || + ioport_read_table[2][start] || ioport_write_table[2][start]); +} + /***********************************************************/ -void cpu_outb(a_pio_addr addr, uint8_t val) +void cpu_outb(pio_addr_t addr, uint8_t val) { LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); + trace_cpu_out(addr, val); ioport_write(0, addr, val); } -void cpu_outw(a_pio_addr addr, uint16_t val) +void cpu_outw(pio_addr_t addr, uint16_t val) { LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); + trace_cpu_out(addr, val); ioport_write(1, addr, val); } -void cpu_outl(a_pio_addr addr, uint32_t val) +void cpu_outl(pio_addr_t addr, uint32_t val) { LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); + trace_cpu_out(addr, val); ioport_write(2, addr, val); } -uint8_t cpu_inb(a_pio_addr addr) +uint8_t cpu_inb(pio_addr_t addr) { uint8_t val; val = ioport_read(0, addr); + trace_cpu_in(addr, val); LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); return val; } -uint16_t cpu_inw(a_pio_addr addr) +uint16_t cpu_inw(pio_addr_t addr) { uint16_t val; val = ioport_read(1, addr); + trace_cpu_in(addr, val); LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); return val; } -uint32_t cpu_inl(a_pio_addr addr) +uint32_t cpu_inl(pio_addr_t addr) { uint32_t val; val = ioport_read(2, addr); + trace_cpu_in(addr, val); LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); return val; }