X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=qemu-tech.texi;h=138e3ce9add9151b70d506b94e6305360a830c23;hb=ef942b795a0e449d4239489eb19b73aa35d12404;hp=6c24d910c31e0533f80cf60dfeb395c6d4af211b;hpb=998a050186aaab43ae0027f7aceba158ed03766b;p=qemu.git

diff --git a/qemu-tech.texi b/qemu-tech.texi
index 6c24d910c..138e3ce9a 100644
--- a/qemu-tech.texi
+++ b/qemu-tech.texi
@@ -1,11 +1,21 @@
 \input texinfo @c -*- texinfo -*-
 @c %**start of header
 @setfilename qemu-tech.info
+
+@documentlanguage en
+@documentencoding UTF-8
+
 @settitle QEMU Internals
 @exampleindent 0
 @paragraphindent 0
 @c %**end of header
 
+@ifinfo
+@direntry
+* QEMU Internals: (qemu-tech).   The QEMU Emulator Internals.
+@end direntry
+@end ifinfo
+
 @iftex
 @titlepage
 @sp 7
@@ -116,8 +126,8 @@ QEMU full system emulation features:
 QEMU uses a full software MMU for maximum portability.
 
 @item
-QEMU can optionally use an in-kernel accelerator, like kqemu and
-kvm. The accelerators execute some of the guest code natively, while
+QEMU can optionally use an in-kernel accelerator, like kvm. The accelerators 
+execute some of the guest code natively, while
 continuing to emulate the rest of the machine.
 
 @item
@@ -363,7 +373,9 @@ look at @code{tcg/README}.
 Lazy evaluation of CPU condition codes (@code{EFLAGS} register on x86)
 is important for CPUs where every instruction sets the condition
 codes. It tends to be less important on conventional RISC systems
-where condition codes are only updated when explicitly requested.
+where condition codes are only updated when explicitly requested. On
+Sparc64, costly update of both 32 and 64 bit condition codes can be
+avoided with lazy evaluation.
 
 Instead of computing the condition codes after each x86 instruction,
 QEMU just stores one operand (called @code{CC_SRC}), the result
@@ -376,8 +388,8 @@ conditional branches.
 @code{CC_OP} is almost never explicitly set in the generated code
 because it is known at translation time.
 
-The lazy condition code evaluation is used on x86, m68k and cris. ARM
-uses a simplified variant for the N and Z flags.
+The lazy condition code evaluation is used on x86, m68k, cris and
+Sparc. ARM uses a simplified variant for the N and Z flags.
 
 @node CPU state optimisations
 @section CPU state optimisations
@@ -504,7 +516,7 @@ timers, especially together with the use of bottom halves (BHs).
 @section Hardware interrupts
 
 In order to be faster, QEMU does not check at every basic block if an
-hardware interrupt is pending. Instead, the user must asynchrously
+hardware interrupt is pending. Instead, the user must asynchronously
 call a specific function to tell that an interrupt is pending. This
 function resets the chaining of the currently executing basic
 block. It ensures that the execution will return soon in the main loop
@@ -536,7 +548,7 @@ Linux kernel does. The @code{sigreturn()} system call is emulated to return
 from the virtual signal handler.
 
 Some signals (such as SIGALRM) directly come from the host. Other
-signals are synthetized from the virtual CPU exceptions such as SIGFPE
+signals are synthesized from the virtual CPU exceptions such as SIGFPE
 when a division by zero is done (see @code{main.c:cpu_loop()}).
 
 The blocked signal mask is still handled by the host Linux kernel so