X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=target-arm%2Ftranslate.c;h=a6647d4f7ba23360efbedde10a70af63781b7dc0;hb=5fafdf24ef2c090c164d4dc89684b3f379dbdd87;hp=364f4eadba9d5e98c0f1dc6582cdef98d70d0b62;hpb=a90b7318ba55b1aed71e299ec965bbd8f393b9b3;p=mirror_qemu.git diff --git a/target-arm/translate.c b/target-arm/translate.c index 364f4eadba..a6647d4f7b 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -1,6 +1,6 @@ /* * ARM translation - * + * * Copyright (c) 2003 Fabrice Bellard * Copyright (c) 2005 CodeSourcery, LLC * Copyright (c) 2007 OpenedHand, Ltd. @@ -116,7 +116,7 @@ const uint8_t table_logic_cc[16] = { 1, /* bic */ 1, /* mvn */ }; - + static GenOpFunc1 *gen_shift_T1_im[4] = { gen_op_shll_T1_im, gen_op_shrl_T1_im, @@ -390,7 +390,7 @@ static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, int extra) { int val, rm; - + if (insn & (1 << 22)) { /* immediate */ val = (insn & 0xf) | ((insn >> 4) & 0xf0); @@ -1784,7 +1784,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) delta_m = 0; delta_d = 0; bank_mask = 0; - + if (veclen > 0) { if (dp) bank_mask = 0xc; @@ -2205,10 +2205,10 @@ static void gen_exception_return(DisasContext *s) static void disas_arm_insn(CPUState * env, DisasContext *s) { unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; - + insn = ldl_code(s->pc); s->pc += 4; - + cond = insn >> 28; if (cond == 0xf){ /* Unconditional instructions. */ @@ -2230,6 +2230,13 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) gen_op_movl_T0_im(val); gen_bx(s); return; + } else if ((insn & 0x0e000f00) == 0x0c000100) { + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + /* iWMMXt register transfer. */ + if (env->cp15.c15_cpar & (1 << 1)) + if (!disas_iwmmxt_insn(env, s, insn)) + return; + } } else if ((insn & 0x0fe00000) == 0x0c400000) { /* Coprocessor double register transfer. */ } else if ((insn & 0x0f000010) == 0x0e000010) { @@ -2325,9 +2332,9 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) /* branch link/exchange thumb (blx) */ val = (uint32_t)s->pc; - gen_op_movl_T0_im(val); - gen_movl_reg_T0(s, 14); + gen_op_movl_T1_im(val); gen_movl_T0_reg(s, rm); + gen_movl_reg_T1(s, 14); gen_bx(s); break; case 0x5: /* saturating add/subtract */ @@ -2396,7 +2403,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { int set_cc, logic_cc, shiftop; - + op1 = (insn >> 21) & 0xf; set_cc = (insn >> 20) & 1; logic_cc = table_logic_cc[op1] & set_cc; @@ -2587,14 +2594,14 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) gen_movl_T1_reg(s, rn); gen_op_addl_T0_T1(); } - if (insn & (1 << 20)) + if (insn & (1 << 20)) gen_op_logic_T0_cc(); gen_movl_reg_T0(s, rd); } else { /* 64 bit mul */ gen_movl_T0_reg(s, rs); gen_movl_T1_reg(s, rm); - if (insn & (1 << 22)) + if (insn & (1 << 22)) gen_op_imull_T0_T1(); else gen_op_mull_T0_T1(); @@ -2605,7 +2612,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) gen_op_addq_lo_T0_T1(rn); gen_op_addq_lo_T0_T1(rd); } - if (insn & (1 << 20)) + if (insn & (1 << 20)) gen_op_logicq_cc(); gen_movl_reg_T0(s, rn); gen_movl_reg_T1(s, rd); @@ -2619,7 +2626,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } else { /* SWP instruction */ rm = (insn) & 0xf; - + gen_movl_T0_reg(s, rm); gen_movl_T1_reg(s, rn); if (insn & (1 << 22)) { @@ -2792,7 +2799,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } rn = (insn >> 16) & 0xf; gen_movl_T1_reg(s, rn); - + /* compute total size */ loaded_base = 0; n = 0; @@ -2837,8 +2844,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } else { /* store */ if (i == 15) { - /* special case: r15 = PC + 12 */ - val = (long)s->pc + 8; + /* special case: r15 = PC + 8 */ + val = (long)s->pc + 4; gen_op_movl_TN_im[0](val); } else if (user) { gen_op_movl_T0_user(i); @@ -2890,7 +2897,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) case 0xb: { int32_t offset; - + /* branch (and link) */ val = (int32_t)s->pc; if (insn & (1 << 24)) { @@ -3493,7 +3500,7 @@ static void disas_thumb_insn(DisasContext *s) val = (uint32_t)s->pc + 2; gen_op_movl_T1_im(val | 1); gen_movl_reg_T1(s, 14); - + val += offset << 1; if (insn & (1 << 12)) { /* bl */ @@ -3516,8 +3523,8 @@ undef: /* generate intermediate code in gen_opc_buf and gen_opparam_buf for basic block 'tb'. If search_pc is TRUE, also generate PC information for each intermediate instruction. */ -static inline int gen_intermediate_code_internal(CPUState *env, - TranslationBlock *tb, +static inline int gen_intermediate_code_internal(CPUState *env, + TranslationBlock *tb, int search_pc) { DisasContext dc1, *dc = &dc1; @@ -3525,10 +3532,10 @@ static inline int gen_intermediate_code_internal(CPUState *env, int j, lj; target_ulong pc_start; uint32_t next_page_start; - + /* generate intermediate code */ pc_start = tb->pc; - + dc->tb = tb; gen_opc_ptr = gen_opc_buf; @@ -3649,7 +3656,6 @@ static inline int gen_intermediate_code_internal(CPUState *env, lj++; while (lj <= j) gen_opc_instr_start[lj++] = 0; - tb->size = 0; } else { tb->size = dc->pc - pc_start; } @@ -3670,7 +3676,7 @@ static const char *cpu_mode_names[16] = { "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", "???", "???", "???", "und", "???", "???", "???", "sys" }; -void cpu_dump_state(CPUState *env, FILE *f, +void cpu_dump_state(CPUState *env, FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...), int flags) { @@ -3702,7 +3708,7 @@ void cpu_dump_state(CPUState *env, FILE *f, psr & (1 << 30) ? 'Z' : '-', psr & (1 << 29) ? 'C' : '-', psr & (1 << 28) ? 'V' : '-', - psr & CPSR_T ? 'T' : 'A', + psr & CPSR_T ? 'T' : 'A', cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); for (i = 0; i < 16; i++) {