X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=target-microblaze%2Ftranslate.c;h=15f1fe5cf0aab02dffd062c5659f2a9b6820ccf1;hb=97b833c5df820acc5c7b3e63c84059857c115c45;hp=1a862d31e31db19e4f3f2df85dc8abf7daaaa5fc;hpb=01e0451a08e0afb9af04783c320d70084cf4e574;p=qemu.git

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 1a862d31e..15f1fe5cf 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -424,10 +424,15 @@ static inline void msr_read(DisasContext *dc, TCGv d)
 
 static inline void msr_write(DisasContext *dc, TCGv v)
 {
+    TCGv t;
+
+    t = tcg_temp_new();
     dc->cpustate_changed = 1;
-    tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
-    /* PVR, we have a processor version register.  */
-    tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
+    /* PVR bit is not writable.  */
+    tcg_gen_andi_tl(t, v, ~(1 << 10));
+    tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
+    tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
+    tcg_temp_free(t);
 }
 
 static void dec_msr(DisasContext *dc)