X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=user-exec.c;h=82bfa66ce303efdfc94701e657674a95b7ce7ea4;hb=8d07d6c46597a885eb38d99cc6fff399ce69cd21;hp=d4a6abb8f5a6cce8fade6dff1061c30710195cf0;hpb=ed7ec8400707fe42f4a0f40db2f2d5827ecea789;p=qemu.git diff --git a/user-exec.c b/user-exec.c index d4a6abb8f..82bfa66ce 100644 --- a/user-exec.c +++ b/user-exec.c @@ -17,9 +17,10 @@ * License along with this library; if not, see . */ #include "config.h" -#include "exec.h" -#include "disas.h" +#include "cpu.h" +#include "disas/disas.h" #include "tcg.h" +#include "qemu/bitops.h" #undef EAX #undef ECX @@ -37,18 +38,19 @@ //#define DEBUG_SIGNAL +static void exception_action(CPUArchState *env1) +{ #if defined(TARGET_I386) -#define EXCEPTION_ACTION \ - raise_exception_err(env->exception_index, env->error_code) + raise_exception_err(env1, env1->exception_index, env1->error_code); #else -#define EXCEPTION_ACTION \ - cpu_loop_exit() + cpu_loop_exit(env1); #endif +} /* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator */ -void cpu_resume_from_signal(CPUState *env1, void *puc) +void cpu_resume_from_signal(CPUArchState *env1, void *puc) { #ifdef __linux__ struct ucontext *uc = puc; @@ -56,10 +58,6 @@ void cpu_resume_from_signal(CPUState *env1, void *puc) struct sigcontext *uc = puc; #endif - env = env1; - - /* XXX: restore cpu registers saved in host registers */ - if (puc) { /* XXX: use siglongjmp ? */ #ifdef __linux__ @@ -72,35 +70,38 @@ void cpu_resume_from_signal(CPUState *env1, void *puc) sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL); #endif } - env->exception_index = -1; - longjmp(env->jmp_env, 1); + env1->exception_index = -1; + siglongjmp(env1->jmp_env, 1); } /* 'pc' is the host PC at which the exception was raised. 'address' is the effective address of the memory exception. 'is_write' is 1 if a write caused the exception and otherwise 0'. 'old_set' is the signal set which should be restored */ -static inline int handle_cpu_signal(unsigned long pc, unsigned long address, +static inline int handle_cpu_signal(uintptr_t pc, unsigned long address, int is_write, sigset_t *old_set, void *puc) { - TranslationBlock *tb; + CPUArchState *env; int ret; - if (cpu_single_env) { - env = cpu_single_env; /* XXX: find a correct solution for multithread */ - } #if defined(DEBUG_SIGNAL) qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", pc, address, is_write, *(unsigned long *)old_set); #endif /* XXX: locking issue */ - if (is_write && page_unprotect(h2g(address), pc, puc)) { + if (is_write && h2g_valid(address) + && page_unprotect(h2g(address), pc, puc)) { return 1; } + /* Convert forcefully to guest address space, invalid addresses + are still valid segv ones */ + address = h2g_nocheck(address); + + env = current_cpu->env_ptr; /* see if it is an MMU fault */ - ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0); + ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX); if (ret < 0) { return 0; /* not an MMU fault */ } @@ -108,17 +109,12 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, return 1; /* the MMU fault was handled without causing real CPU fault */ } /* now we have a real cpu fault */ - tb = tb_find_pc(pc); - if (tb) { - /* the PC is inside the translated code. It means that we have - a virtual CPU fault */ - cpu_restore_state(tb, env, pc); - } + cpu_restore_state(env, pc); /* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */ sigprocmask(SIG_SETMASK, old_set, NULL); - EXCEPTION_ACTION; + exception_action(env); /* never comes here */ return 1; @@ -446,18 +442,36 @@ int cpu_signal_handler(int host_signum, void *pinfo, unsigned long pc; int is_write; -#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) +#if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) pc = uc->uc_mcontext.gregs[R15]; #else pc = uc->uc_mcontext.arm_pc; #endif - /* XXX: compute is_write */ - is_write = 0; + + /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or + * later processor; on v5 we will always report this as a read). + */ + is_write = extract32(uc->uc_mcontext.error_code, 11, 1); return handle_cpu_signal(pc, (unsigned long)info->si_addr, is_write, &uc->uc_sigmask, puc); } +#elif defined(__aarch64__) + +int cpu_signal_handler(int host_signum, void *pinfo, + void *puc) +{ + siginfo_t *info = pinfo; + struct ucontext *uc = puc; + uint64_t pc; + int is_write = 0; /* XXX how to determine? */ + + pc = uc->uc_mcontext.pc; + return handle_cpu_signal(pc, (uint64_t)info->si_addr, + is_write, &uc->uc_sigmask, puc); +} + #elif defined(__mc68000) int cpu_signal_handler(int host_signum, void *pinfo, @@ -585,7 +599,7 @@ int cpu_signal_handler(int host_signum, void *pinfo, int cpu_signal_handler(int host_signum, void *pinfo, void *puc) { - struct siginfo *info = pinfo; + siginfo_t *info = pinfo; struct ucontext *uc = puc; unsigned long pc = uc->uc_mcontext.sc_iaoq[0]; uint32_t insn = *(uint32_t *)pc; @@ -627,47 +641,3 @@ int cpu_signal_handler(int host_signum, void *pinfo, #error host CPU specific signal handler needed #endif - -#if defined(TARGET_I386) - -void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) -{ - CPUX86State *saved_env; - - saved_env = env; - env = s; - if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { - selector &= 0xffff; - cpu_x86_load_seg_cache(env, seg_reg, selector, - (selector << 4), 0xffff, 0); - } else { - helper_load_seg(seg_reg, selector); - } - env = saved_env; -} - -void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32) -{ - CPUX86State *saved_env; - - saved_env = env; - env = s; - - helper_fsave(ptr, data32); - - env = saved_env; -} - -void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32) -{ - CPUX86State *saved_env; - - saved_env = env; - env = s; - - helper_frstor(ptr, data32); - - env = saved_env; -} - -#endif /* TARGET_I386 */