]> git.proxmox.com Git - mirror_qemu.git/commit - target/riscv/cpu_bits.h
target/riscv: Implement mcountinhibit CSR
authorAtish Patra <atish.patra@wdc.com>
Mon, 20 Jun 2022 23:15:55 +0000 (16:15 -0700)
committerAlistair Francis <alistair@alistair23.me>
Sun, 3 Jul 2022 00:03:20 +0000 (10:03 +1000)
commitb1675eeb3e6e38b042a23a9647559c9c548c733d
treebc5b0e5aa6ee899d84d2f2d63c172f315f618c3c
parent18d6d89efc60f1c030c4a8a22816d2d911ece105
target/riscv: Implement mcountinhibit CSR

As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/csr.c
target/riscv/machine.c