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target/riscv: Fix shift count overflow
authordemin.han <demin.han@starfivetech.com>
Sun, 25 Feb 2024 17:41:14 +0000 (01:41 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 8 Mar 2024 10:48:03 +0000 (20:48 +1000)
commit938dd05ea1f3a9e3c713b1d73dc2992d62efb830
tree51534578d6023330daf4fc353dc8e78849815f4etree
parenta506c4289dd05b3134a1b6eb0b506eaee81e224dcommit | diff
target/riscv: Fix shift count overflow

The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
and results in wrong vill.

Signed-off-by: demin.han <demin.han@starfivetech.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240225174114.5298-1-demin.han@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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