Correctness issues:
- some eflags manipulation incorrectly reset the bit 0x2.
-- rework eflags optimization (will be a consequence of TCG port)
- SVM: rework the implementation: simplify code, move most intercept
tests as dynamic, correct segment access, verify exception safety,
cpu save/restore, SMM save/restore.
-- x86_64: fxsave/fxrestore intel/amd differences
- x86_64: lcall/ljmp intel/amd differences ?
-- x86_64: cmpxchgl intel/amd differences ?
-- x86_64: cmovl intel/amd differences ?
-- cmpxchg16b + cmpxchg8b cpuid test
-- x86: monitor invalid
- better code fetch (different exception handling + CS.limit support)
- user/kernel PUSHL/POPL in helper.c
- add missing cpuid tests
Optimizations/Features:
-- finish TCG port
- add SVM nested paging support
- add VMX support
- add AVX support
- add SSE5 support
+- fxsave/fxrstor AMD extensions
+- improve monitor/mwait support
- faster EFLAGS update: consider SZAP, C, O can be updated separately
with a bit field in CC_OP and more state variables.
- evaluate x87 stack pointer statically
int cpuid_features;
int cpuid_ext_features;
int cpuid_ext2_features;
+ int cpuid_ext3_features;
} DisasContext;
static void gen_eob(DisasContext *s);
}
break;
case 0x9e: /* sahf */
- if (CODE64(s))
+ if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
if (s->cc_op != CC_OP_DYNAMIC)
s->cc_op = CC_OP_EFLAGS;
break;
case 0x9f: /* lahf */
- if (CODE64(s))
+ if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
goto illegal_op;
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
dc->cpuid_features = env->cpuid_features;
dc->cpuid_ext_features = env->cpuid_ext_features;
dc->cpuid_ext2_features = env->cpuid_ext2_features;
+ dc->cpuid_ext3_features = env->cpuid_ext3_features;
#ifdef TARGET_X86_64
dc->lma = (flags >> HF_LMA_SHIFT) & 1;
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;