epoll_pwait=yes
fi
+# check for sendfile support
+sendfile=no
+cat > $TMPC << EOF
+#include <sys/sendfile.h>
+
+int main(void)
+{
+ return sendfile(0, 0, 0, 0);
+}
+EOF
+if compile_prog "" "" ; then
+ sendfile=yes
+fi
+
# Check if tools are available to build documentation.
if test "$docs" != "no" ; then
if has makeinfo && has pod2man; then
if test "$epoll_pwait" = "yes" ; then
echo "CONFIG_EPOLL_PWAIT=y" >> $config_host_mak
fi
+if test "$sendfile" = "yes" ; then
+ echo "CONFIG_SENDFILE=y" >> $config_host_mak
+fi
if test "$inotify" = "yes" ; then
echo "CONFIG_INOTIFY=y" >> $config_host_mak
fi
int cpu_exec(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
+#if !(defined(CONFIG_USER_ONLY) && \
+ (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
int ret, interrupt_request;
TranslationBlock *tb;
uint8_t *tc_ptr;
tcg_target_ulong next_tb;
- if (env->halted) {
+ if (cpu->halted) {
if (!cpu_has_work(cpu)) {
return EXCP_HALTED;
}
- env->halted = 0;
+ cpu->halted = 0;
}
cpu_single_env = env;
which will be handled outside the cpu execution
loop */
#if defined(TARGET_I386)
- do_interrupt(env);
+ cc->do_interrupt(cpu);
#endif
ret = env->exception_index;
break;
#else
- do_interrupt(env);
+ cc->do_interrupt(cpu);
env->exception_index = -1;
#endif
}
next_tb = 0; /* force lookup of first TB */
for(;;) {
- interrupt_request = env->interrupt_request;
+ interrupt_request = cpu->interrupt_request;
if (unlikely(interrupt_request)) {
if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
/* Mask out external interrupts for this step. */
interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
}
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
- env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
+ cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
env->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
}
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HALT) {
- env->interrupt_request &= ~CPU_INTERRUPT_HALT;
- env->halted = 1;
+ cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
+ cpu->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
#if defined(TARGET_I386)
#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_POLL) {
- env->interrupt_request &= ~CPU_INTERRUPT_POLL;
+ cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
apic_poll_irq(env->apic_state);
}
#endif
!(env->hflags & HF_SMM_MASK)) {
cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
0);
- env->interrupt_request &= ~CPU_INTERRUPT_SMI;
+ cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
do_smm_enter(env);
next_tb = 0;
} else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
!(env->hflags2 & HF2_NMI_MASK)) {
- env->interrupt_request &= ~CPU_INTERRUPT_NMI;
+ cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
env->hflags2 |= HF2_NMI_MASK;
do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
next_tb = 0;
} else if (interrupt_request & CPU_INTERRUPT_MCE) {
- env->interrupt_request &= ~CPU_INTERRUPT_MCE;
+ cpu->interrupt_request &= ~CPU_INTERRUPT_MCE;
do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
next_tb = 0;
} else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
int intno;
cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
0);
- env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
+ cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD |
+ CPU_INTERRUPT_VIRQ);
intno = cpu_get_pic_interrupt(env);
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
- env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
+ cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
next_tb = 0;
#endif
}
}
if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env);
- if (env->pending_interrupts == 0)
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ if (env->pending_interrupts == 0) {
+ cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ }
next_tb = 0;
}
#elif defined(TARGET_LM32)
if ((interrupt_request & CPU_INTERRUPT_HARD)
&& (env->ie & IE_IE)) {
env->exception_index = EXCP_IRQ;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_MICROBLAZE)
&& !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
&& !(env->iflags & (D_FLAG | IMM_FLAG))) {
env->exception_index = EXCP_IRQ;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_MIPS)
/* Raise it */
env->exception_index = EXCP_EXT_INTERRUPT;
env->error_code = 0;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_OPENRISC)
}
if (idx >= 0) {
env->exception_index = idx;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
}
cpu_pil_allowed(env, pil)) ||
type != TT_EXTINT) {
env->exception_index = env->interrupt_index;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
}
if (interrupt_request & CPU_INTERRUPT_FIQ
&& !(env->uncached_cpsr & CPSR_F)) {
env->exception_index = EXCP_FIQ;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
/* ARMv7-M interrupt return works by loading a magic value
&& ((IS_M(env) && env->regs[15] < 0xfffffff0)
|| !(env->uncached_cpsr & CPSR_I))) {
env->exception_index = EXCP_IRQ;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HARD
&& !(env->uncached_asr & ASR_I)) {
env->exception_index = UC32_EXCP_INTR;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_SH4)
if (interrupt_request & CPU_INTERRUPT_HARD) {
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_ALPHA)
if (idx >= 0) {
env->exception_index = idx;
env->error_code = 0;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
}
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
env->exception_index = EXCP_IRQ;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
if (interrupt_request & CPU_INTERRUPT_NMI) {
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
env->exception_index = EXCP_NMI;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
}
#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
(env->psw.mask & PSW_MASK_EXT)) {
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_XTENSA)
if (interrupt_request & CPU_INTERRUPT_HARD) {
env->exception_index = EXC_IRQ;
- do_interrupt(env);
+ cc->do_interrupt(cpu);
next_tb = 0;
}
#endif
/* Don't use the cached interrupt_request value,
do_interrupt may have updated the EXITTB flag. */
- if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
- env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
+ if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
+ cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
/* ensure that no TB jump will be modified as
the program flow was changed */
next_tb = 0;
if (cpu->stopped || !runstate_is_running()) {
return true;
}
- if (!env->halted || qemu_cpu_has_work(cpu) ||
+ if (!cpu->halted || qemu_cpu_has_work(cpu) ||
kvm_async_interrupts_enabled()) {
return false;
}
info->value = g_malloc0(sizeof(*info->value));
info->value->CPU = cpu->cpu_index;
info->value->current = (env == first_cpu);
- info->value->halted = env->halted;
+ info->value->halted = cpu->halted;
info->value->thread_id = cpu->thread_id;
#if defined(TARGET_I386)
info->value->has_pc = true;
cpu_index = 0;
}
- for (env = first_cpu; env; env = env->next_cpu) {
- cpu = ENV_GET_CPU(env);
- if (cpu_index == cpu->cpu_index) {
- break;
- }
- }
-
- if (env == NULL) {
+ cpu = qemu_get_cpu(cpu_index);
+ if (cpu == NULL) {
error_set(errp, QERR_INVALID_PARAMETER_VALUE, "cpu-index",
"a CPU number");
return;
}
+ env = cpu->env_ptr;
f = fopen(filename, "wb");
if (!f) {
for (env = first_cpu; env != NULL; env = env->next_cpu) {
if (!env->apic_state) {
- cpu_interrupt(env, CPU_INTERRUPT_NMI);
+ cpu_interrupt(CPU(x86_env_get_cpu(env)), CPU_INTERRUPT_NMI);
} else {
apic_deliver_nmi(env->apic_state);
}
#endif
}
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
static int cpu_common_post_load(void *opaque, int version_id)
{
- CPUArchState *env = opaque;
+ CPUState *cpu = opaque;
/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
version_id is increased. */
- env->interrupt_request &= ~0x01;
- tlb_flush(env, 1);
+ cpu->interrupt_request &= ~0x01;
+ tlb_flush(cpu->env_ptr, 1);
return 0;
}
.minimum_version_id_old = 1,
.post_load = cpu_common_post_load,
.fields = (VMStateField []) {
- VMSTATE_UINT32(halted, CPUArchState),
- VMSTATE_UINT32(interrupt_request, CPUArchState),
+ VMSTATE_UINT32(halted, CPUState),
+ VMSTATE_UINT32(interrupt_request, CPUState),
VMSTATE_END_OF_LIST()
}
};
+#else
+#define vmstate_cpu_common vmstate_dummy
#endif
CPUState *qemu_get_cpu(int index)
env = env->next_cpu;
}
- return cpu;
+ return env ? cpu : NULL;
}
void cpu_exec_init(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
CPUArchState **penv;
int cpu_index;
#if defined(CONFIG_USER_ONLY)
cpu_list_unlock();
#endif
+ vmstate_register(NULL, cpu_index, &vmstate_cpu_common, cpu);
#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
- vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
+ assert(cc->vmsd == NULL);
#endif
+ if (cc->vmsd != NULL) {
+ vmstate_register(NULL, cpu_index, cc->vmsd, cpu);
+ }
}
#if defined(TARGET_HAS_ICE)
#endif
}
-void cpu_reset_interrupt(CPUArchState *env, int mask)
-{
- env->interrupt_request &= ~mask;
-}
-
void cpu_exit(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
/* We re-entered the check after replacing the TB. Now raise
* the debug interrupt so that is will trigger after the
* current instruction. */
- cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
+ cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG);
return;
}
vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
cpu_synchronize_state(env);
len = snprintf((char *)mem_buf, sizeof(mem_buf),
"CPU#%d [%s]", cpu->cpu_index,
- env->halted ? "halted " : "running");
+ cpu->halted ? "halted " : "running");
memtohex(buf, mem_buf, len);
put_packet(s, buf);
}
{
/* If there are any non-masked interrupts, tell the cpu. */
if (cpu != NULL) {
- CPUAlphaState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
if (req) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
}
for (i = 0; i < 4; ++i) {
AlphaCPU *cpu = s->cchip.cpu[i];
if (cpu != NULL) {
- CPUAlphaState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
/* IPI can be either cleared or set by the write. */
if (newval & (1 << (i + 8))) {
- cpu_interrupt(env, CPU_INTERRUPT_SMP);
+ cpu_interrupt(cs, CPU_INTERRUPT_SMP);
} else {
- cpu_reset_interrupt(env, CPU_INTERRUPT_SMP);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP);
}
/* ITI can only be cleared by the write. */
if ((newval & (1 << (i + 4))) == 0) {
- cpu_reset_interrupt(env, CPU_INTERRUPT_TIMER);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER);
}
}
}
/* Set the ITI bit for this cpu. */
s->cchip.misc |= 1 << (i + 4);
/* And signal the interrupt. */
- cpu_interrupt(&cpu->env, CPU_INTERRUPT_TIMER);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER);
}
}
}
/* Set the ITI bit for this cpu. */
s->cchip.misc |= 1 << (cpu + 4);
- cpu_interrupt(&s->cchip.cpu[cpu]->env, CPU_INTERRUPT_TIMER);
+ cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER);
}
PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
switch ((lvt >> 8) & 7) {
case APIC_DM_SMI:
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
break;
case APIC_DM_NMI:
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
break;
case APIC_DM_EXTINT:
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
break;
case APIC_DM_FIXED:
reset_bit(s->irr, lvt & 0xff);
/* fall through */
case APIC_DM_EXTINT:
- cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
break;
}
}
case APIC_DM_SMI:
foreach_apic(apic_iter, deliver_bitmask,
- cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI)
+ cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
);
return;
case APIC_DM_NMI:
foreach_apic(apic_iter, deliver_bitmask,
- cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI)
+ cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
);
return;
case APIC_DM_INIT:
/* normal INIT IPI sent to processors */
foreach_apic(apic_iter, deliver_bitmask,
- cpu_interrupt(&apic_iter->cpu->env,
+ cpu_interrupt(CPU(apic_iter->cpu),
CPU_INTERRUPT_INIT)
);
return;
/* signal the CPU if an irq is pending */
static void apic_update_irq(APICCommonState *s)
{
- CPUState *cpu = CPU(s->cpu);
+ CPUState *cpu;
if (!(s->spurious_vec & APIC_SV_ENABLE)) {
return;
}
+ cpu = CPU(s->cpu);
if (!qemu_cpu_is_self(cpu)) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL);
+ cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
} else if (apic_irq_pending(s) > 0) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
}
}
static void apic_startup(APICCommonState *s, int vector_num)
{
s->sipi_vector = vector_num;
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
}
void apic_sipi(DeviceState *d)
{
APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
- cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
+ cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
if (!s->wait_for_sipi)
return;
omap_clk clk;
if (value & (1 << 11)) { /* SETARM_IDLE */
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
}
if (!(value & (1 << 10))) /* WKUP_MODE */
qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ CPUState *cpu = CPU(s->cpu);
if (size != 2) {
return omap_badwidth_read16(opaque, addr);
return s->clkm.dsp_rstct2;
case 0x18: /* DSP_SYSST */
+ cpu = CPU(s->cpu);
return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
- (s->cpu->env.halted << 6); /* Quite useless... */
+ (cpu->halted << 6); /* Quite useless... */
}
OMAP_BAD_REG(addr);
void omap_mpu_wakeup(void *opaque, int irq, int req)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
+ CPUState *cpu = CPU(mpu->cpu);
- if (mpu->cpu->env.halted) {
- cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB);
+ if (cpu->halted) {
+ cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}
static void arm_pic_cpu_handler(void *opaque, int irq, int level)
{
ARMCPU *cpu = opaque;
- CPUARMState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
switch (irq) {
case ARM_PIC_CPU_IRQ:
- if (level)
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
- else
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ if (level) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
break;
case ARM_PIC_CPU_FIQ:
- if (level)
- cpu_interrupt(env, CPU_INTERRUPT_FIQ);
- else
- cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
+ if (level) {
+ cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
+ }
break;
default:
hw_error("arm_pic_cpu_handler: Bad interrupt line %d\n", irq);
case 1:
/* Idle */
if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
break;
}
/* Fall through. */
case 2:
/* Deep-Idle */
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HALT);
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
goto message;
#endif
/* Suspend */
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(arm_env_get_cpu(cpu_single_env)),
+ CPU_INTERRUPT_HALT);
goto message;
static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
+ CPUState *cpu = CPU(s->cpu);
int bank;
uint32_t mask;
pxa2xx_gpio_irq_update(s);
/* Wake-up GPIOs */
- if (s->cpu->env.halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
+ if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
+ cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}
{
uint32_t mask[2];
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
+ CPUState *cpu = CPU(s->cpu);
- if (s->cpu->env.halted) {
+ if (cpu->halted) {
mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
if (mask[0] || mask[1]) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
+ cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
}
}
mask[1] = s->int_pending[1] & s->int_enabled[1];
if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
+ cpu_interrupt(cpu, CPU_INTERRUPT_FIQ);
} else {
- cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);
+ cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);
}
if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {
- cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
} else {
- cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
}
}
static void cris_pic_cpu_handler(void *opaque, int irq, int level)
{
- CPUCRISState *env = (CPUCRISState *)opaque;
+ CRISCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
- if (level)
- cpu_interrupt(env, type);
- else
- cpu_reset_interrupt(env, type);
+ if (level) {
+ cpu_interrupt(cs, type);
+ } else {
+ cpu_reset_interrupt(cs, type);
+ }
}
qemu_irq *cris_pic_init_cpu(CPUCRISState *env)
{
- return qemu_allocate_irqs(cris_pic_cpu_handler, env, 2);
+ return qemu_allocate_irqs(cris_pic_cpu_handler, cris_env_get_cpu(env), 2);
}
env = env->next_cpu;
}
} else {
- if (level)
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
- else
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ if (level) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
}
}
void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
{
- CPUX86State *s = opaque;
+ X86CPU *cpu = opaque;
if (level) {
- cpu_interrupt(s, CPU_INTERRUPT_SMI);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
}
}
if (pci_enabled && acpi_enabled) {
i2c_bus *smbus;
- smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
+ smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt,
+ x86_env_get_cpu(first_cpu), 1);
/* TODO: Populate SPD eeprom data. */
smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
gsi[9], *smi_irq,
const char *kernel_cmdline = args->kernel_cmdline;
const char *initrd_filename = args->initrd_filename;
X86CPU *cpu;
- CPUX86State *env;
+ CPUState *cs;
DriveInfo *dinfo;
int i;
#endif
}
cpu = cpu_x86_init(cpu_model);
- env = &cpu->env;
- env->halted = 1;
+ cs = CPU(cpu);
+ cs->halted = 1;
/* Initialize backend core & drivers */
if (xen_be_init() != 0) {
static void cpu_irq_handler(void *opaque, int irq, int level)
{
- CPULM32State *env = opaque;
+ LM32CPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
/* create irq lines */
- cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
+ cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
env->pic_state = lm32_pic_init(*cpu_irq);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(env->pic_state, i);
static void cpu_irq_handler(void *opaque, int irq, int level)
{
- CPULM32State *env = opaque;
+ LM32CPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
0x00, 0x89, 0x00, 0x1d, 1);
/* create irq lines */
- cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
+ cpu_irq = qemu_allocate_irqs(cpu_irq_handler, cpu, 1);
env->pic_state = lm32_pic_init(*cpu_irq);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(env->pic_state, i);
/* SMI_EN = PMBASE + 30. SMI control and enable register */
if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
- cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
+ cpu_interrupt(CPU(x86_env_get_cpu(first_cpu)), CPU_INTERRUPT_SMI);
}
}
static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
{
- CPUMBState *env = (CPUMBState *)opaque;
+ MicroBlazeCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
- if (level)
- cpu_interrupt(env, type);
- else
- cpu_reset_interrupt(env, type);
+ if (level) {
+ cpu_interrupt(cs, type);
+ } else {
+ cpu_reset_interrupt(cs, type);
+ }
}
qemu_irq *microblaze_pic_init_cpu(CPUMBState *env)
{
- return qemu_allocate_irqs(microblaze_pic_cpu_handler, env, 2);
+ return qemu_allocate_irqs(microblaze_pic_cpu_handler, mb_env_get_cpu(env),
+ 2);
}
static void cpu_mips_irq_request(void *opaque, int irq, int level)
{
- CPUMIPSState *env = (CPUMIPSState *)opaque;
+ MIPSCPU *cpu = opaque;
+ CPUMIPSState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
if (irq < 0 || irq > 7)
return;
}
if (env->CP0_Cause & CP0Ca_IP_mask) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
qemu_irq *qi;
int i;
- qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
+ qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8);
for (i = 0; i < 8; i++) {
env->irq[i] = qi[i];
}
if ((cpu->env.ttmr & TTMR_IE) &&
qemu_timer_expired(cpu->env.timer, qemu_get_clock_ns(vm_clock))) {
+ CPUState *cs = CPU(cpu);
+
cpu->env.ttmr |= TTMR_IP;
- cpu->env.interrupt_request |= CPU_INTERRUPT_TIMER;
+ cs->interrupt_request |= CPU_INTERRUPT_TIMER;
}
switch (cpu->env.ttmr & TTMR_M) {
static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
{
OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
+ CPUState *cs = CPU(cpu);
int i;
uint32_t irq_bit = 1 << irq;
for (i = 0; i < 32; i++) {
if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
- cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
- cpu_reset_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
cpu->env.picsr &= ~(1 << i);
}
}
static void ppce500_cpu_reset_sec(void *opaque)
{
PowerPCCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- cpu_reset(CPU(cpu));
+ cpu_reset(cs);
/* Secondary CPU starts in halted state for now. Needs to change when
implementing non-kernel boot. */
- env->halted = 1;
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
}
static void ppce500_cpu_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
struct boot_info *bi = env->load_info;
- cpu_reset(CPU(cpu));
+ cpu_reset(cs);
/* Set initial guest state. */
- env->halted = 0;
+ cs->halted = 0;
env->gpr[1] = (16<<20) - 8;
env->gpr[3] = bi->dt_base;
env->nip = bi->entry;
void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
{
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
unsigned int old_pending = env->pending_interrupts;
if (level) {
env->pending_interrupts |= 1 << n_IRQ;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
env->pending_interrupts &= ~(1 << n_IRQ);
- if (env->pending_interrupts == 0)
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ if (env->pending_interrupts == 0) {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
}
if (old_pending != env->pending_interrupts) {
LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
"req %08x\n", __func__, env, n_IRQ, level,
- env->pending_interrupts, env->interrupt_request);
+ env->pending_interrupts, CPU(cpu)->interrupt_request);
}
/* PowerPC 6xx / 7xx internal IRQ controller */
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
+ CPUState *cs = CPU(cpu);
+
switch (pin) {
case PPC6xx_INPUT_TBEN:
/* Level sensitive - active high */
/* XXX: Note that the only way to restart the CPU is to reset it */
if (level) {
LOG_IRQ("%s: stop the CPU\n", __func__);
- env->halted = 1;
+ cs->halted = 1;
}
break;
case PPC6xx_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
LOG_IRQ("%s: reset the CPU\n", __func__);
- cpu_interrupt(env, CPU_INTERRUPT_RESET);
+ cpu_interrupt(cs, CPU_INTERRUPT_RESET);
}
break;
case PPC6xx_INPUT_SRESET:
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
+ CPUState *cs = CPU(cpu);
+
switch (pin) {
case PPC970_INPUT_INT:
/* Level sensitive - active high */
/* XXX: TODO: relay the signal to CKSTP_OUT pin */
if (level) {
LOG_IRQ("%s: stop the CPU\n", __func__);
- env->halted = 1;
+ cs->halted = 1;
} else {
LOG_IRQ("%s: restart the CPU\n", __func__);
- env->halted = 0;
- qemu_cpu_kick(CPU(cpu));
+ cs->halted = 0;
+ qemu_cpu_kick(cs);
}
break;
case PPC970_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_RESET);
+ cpu_interrupt(cs, CPU_INTERRUPT_RESET);
}
break;
case PPC970_INPUT_SRESET:
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
+ CPUState *cs = CPU(cpu);
+
switch (pin) {
case PPC40x_INPUT_RESET_SYS:
if (level) {
/* Level sensitive - active low */
if (level) {
LOG_IRQ("%s: stop the CPU\n", __func__);
- env->halted = 1;
+ cs->halted = 1;
} else {
LOG_IRQ("%s: restart the CPU\n", __func__);
- env->halted = 0;
- qemu_cpu_kick(CPU(cpu));
+ cs->halted = 0;
+ qemu_cpu_kick(cs);
}
break;
case PPC40x_INPUT_DEBUG:
target_ulong dbsr;
printf("Reset PowerPC core\n");
- cpu_interrupt(env, CPU_INTERRUPT_RESET);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
dbsr |= 0x00000100;
target_ulong dbsr;
printf("Reset PowerPC chip\n");
- cpu_interrupt(env, CPU_INTERRUPT_RESET);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
/* XXX: TODO reset all internal peripherals */
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
map_start = ldq_p(&curspin->addr) & ~(map_size - 1);
mmubooke_create_initial_mapping(env, 0, map_start, map_size);
- env->halted = 0;
+ cpu->halted = 0;
env->exception_index = -1;
cpu->stopped = false;
qemu_cpu_kick(cpu);
static void ppc_spapr_reset(void)
{
+ CPUState *first_cpu_cpu;
+
/* Reset the hash table & recalc the RMA */
spapr_reset_htab(spapr);
spapr->rtas_size);
/* Set up the entry state */
+ first_cpu_cpu = CPU(first_cpu);
first_cpu->gpr[3] = spapr->fdt_addr;
first_cpu->gpr[5] = 0;
- first_cpu->halted = 0;
+ first_cpu_cpu->halted = 0;
first_cpu->nip = spapr->entry_point;
}
static void spapr_cpu_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- cpu_reset(CPU(cpu));
+ cpu_reset(cs);
/* All CPUs start halted. CPU0 is unhalted from the machine level
* reset code and the rest are explicitly started up by the guest
* using an RTAS call */
- env->halted = 1;
+ cs->halted = 1;
env->spr[SPR_HIOR] = 0;
env->msr |= (1ULL << MSR_EE);
hreg_compute_hflags(env);
if (!cpu_has_work(cs)) {
- env->halted = 1;
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
cs->exit_request = 1;
}
continue;
}
- if (env->halted) {
+ if (cpu->halted) {
rtas_st(rets, 1, 0);
} else {
rtas_st(rets, 1, 2);
continue;
}
- if (!env->halted) {
+ if (!cpu->halted) {
rtas_st(rets, 0, -1);
return;
}
env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
env->nip = start;
env->gpr[3] = r3;
- env->halted = 0;
+ cpu->halted = 0;
qemu_cpu_kick(cpu);
void s390_add_running_cpu(S390CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUS390XState *env = &cpu->env;
- if (env->halted) {
+ if (cs->halted) {
s390_running_cpus++;
- env->halted = 0;
+ cs->halted = 0;
env->exception_index = -1;
}
}
unsigned s390_del_running_cpu(S390CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUS390XState *env = &cpu->env;
- if (env->halted == 0) {
+ if (cs->halted == 0) {
assert(s390_running_cpus >= 1);
s390_running_cpus--;
- env->halted = 1;
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
}
return s390_running_cpus;
for (i = 0; i < smp_cpus; i++) {
S390CPU *cpu;
+ CPUState *cs;
cpu = cpu_s390x_init(cpu_model);
+ cs = CPU(cpu);
ipi_states[i] = cpu;
- cpu->env.halted = 1;
+ cs->halted = 1;
cpu->env.exception_index = EXCP_HLT;
cpu->env.storage_keys = storage_keys;
}
static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
{
SH7750State *s = opaque;
+ SuperHCPUClass *scc;
switch (addr) {
case SH7750_BCR1_A7:
case SH7750_CCR_A7:
return s->ccr;
case 0x1f000030: /* Processor version */
- return s->cpu->pvr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->pvr;
case 0x1f000040: /* Cache version */
- return s->cpu->cvr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->cvr;
case 0x1f000044: /* Processor revision */
- return s->cpu->prr;
+ scc = SUPERH_CPU_GET_CLASS(s->cpu);
+ return scc->prr;
default:
error_access("long read", addr);
abort();
pending_changed = 1;
if (pending_changed) {
+ CPUState *cpu = CPU(sh_env_get_cpu(first_cpu));
if (source->pending) {
source->parent->pending++;
- if (source->parent->pending == 1)
- cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
- }
- else {
+ if (source->parent->pending == 1) {
+ cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
+ }
+ } else {
source->parent->pending--;
- if (source->parent->pending == 0)
- cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
+ if (source->parent->pending == 0) {
+ cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
+ }
}
}
static void main_cpu_reset(void *opaque)
{
ResetData *s = (ResetData *)opaque;
+ CPUState *cpu = CPU(s->cpu);
CPUSPARCState *env = &s->cpu->env;
- cpu_reset(CPU(s->cpu));
+ cpu_reset(cpu);
- env->halted = 0;
+ cpu->halted = 0;
env->pc = s->entry;
env->npc = s->entry + 4;
}
static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
{
CPUSPARCState *env = (CPUSPARCState *)opaque;
+ CPUState *cs;
assert(env != NULL);
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
+ cs = CPU(sparc_env_get_cpu(env));
trace_leon3_set_irq(i);
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
+ cs = CPU(sparc_env_get_cpu(env));
trace_leon3_reset_irq(env->interrupt_index & 15);
env->interrupt_index = 0;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
void cpu_check_irqs(CPUSPARCState *env)
{
+ CPUState *cs;
+
if (env->pil_in && (env->interrupt_index == 0 ||
(env->interrupt_index & ~15) == TT_EXTINT)) {
unsigned int i;
env->interrupt_index = TT_EXTINT | i;
if (old_interrupt != env->interrupt_index) {
+ cs = CPU(sparc_env_get_cpu(env));
trace_sun4m_cpu_interrupt(i);
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
}
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
+ cs = CPU(sparc_env_get_cpu(env));
trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
env->interrupt_index = 0;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
static void cpu_kick_irq(SPARCCPU *cpu)
{
CPUSPARCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
- env->halted = 0;
+ cs->halted = 0;
cpu_check_irqs(env);
- qemu_cpu_kick(CPU(cpu));
+ qemu_cpu_kick(cs);
}
static void cpu_set_irq(void *opaque, int irq, int level)
static void main_cpu_reset(void *opaque)
{
SPARCCPU *cpu = opaque;
- CPUSPARCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
- cpu_reset(CPU(cpu));
- env->halted = 0;
+ cpu_reset(cs);
+ cs->halted = 0;
}
static void secondary_cpu_reset(void *opaque)
{
SPARCCPU *cpu = opaque;
- CPUSPARCState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
- cpu_reset(CPU(cpu));
- env->halted = 1;
+ cpu_reset(cs);
+ cs->halted = 1;
}
static void cpu_halt_signal(void *opaque, int irq, int level)
{
- if (level && cpu_single_env)
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
+ if (level && cpu_single_env) {
+ cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)),
+ CPU_INTERRUPT_HALT);
+ }
}
static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
static void cpu_devinit(const char *cpu_model, unsigned int id,
uint64_t prom_addr, qemu_irq **cpu_irqs)
{
+ CPUState *cs;
SPARCCPU *cpu;
CPUSPARCState *env;
qemu_register_reset(main_cpu_reset, cpu);
} else {
qemu_register_reset(secondary_cpu_reset, cpu);
- env->halted = 1;
+ cs = CPU(cpu);
+ cs->halted = 1;
}
*cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
env->prom_addr = prom_addr;
void cpu_check_irqs(CPUSPARCState *env)
{
+ CPUState *cs;
uint32_t pil = env->pil_in |
(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
if (env->ivec_status & 0x20) {
return;
}
+ cs = CPU(sparc_env_get_cpu(env));
/* check if TM or SM in SOFTINT are set
setting these also causes interrupt 14 */
if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
/* The bit corresponding to psrpil is (1<< psrpil), the next bit
is (2 << psrpil). */
if (pil < (2 << env->psrpil)){
- if (env->interrupt_request & CPU_INTERRUPT_HARD) {
+ if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
env->interrupt_index);
env->interrupt_index = 0;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
return;
}
env->interrupt_index = new_interrupt;
CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
old_interrupt, new_interrupt);
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
break;
}
}
- } else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
+ } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
"current interrupt %x\n",
pil, env->pil_in, env->softint, env->interrupt_index);
env->interrupt_index = 0;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
static void cpu_kick_irq(SPARCCPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUSPARCState *env = &cpu->env;
- env->halted = 0;
+ cs->halted = 0;
cpu_check_irqs(env);
- qemu_cpu_kick(CPU(cpu));
+ qemu_cpu_kick(cs);
}
static void cpu_set_ivec_irq(void *opaque, int irq, int level)
{
SPARCCPU *cpu = opaque;
CPUSPARCState *env = &cpu->env;
+ CPUState *cs;
if (level) {
if (!(env->ivec_status & 0x20)) {
CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
- env->halted = 0;
+ cs = CPU(cpu);
+ cs->halted = 0;
env->interrupt_index = TT_IVEC;
env->ivec_status |= 0x20;
env->ivec_data[0] = (0x1f << 6) | irq;
env->ivec_data[1] = 0;
env->ivec_data[2] = 0;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
} else {
if (env->ivec_status & 0x20) {
CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
+ cs = CPU(cpu);
env->ivec_status &= ~0x20;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
}
static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
{
- CPUUniCore32State *env = opaque;
+ UniCore32CPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
assert(irq == 0);
if (level) {
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
int i;
/* Initialize interrupt controller */
- cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
+ cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler,
+ uc32_env_get_cpu(env), 1);
dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);
void check_interrupts(CPUXtensaState *env)
{
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
int minlevel = xtensa_get_cintlevel(env);
uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
int level;
/* If the CPU is halted advance CCOUNT according to the vm_clock time
* elapsed since the moment when it was advanced last time.
*/
- if (env->halted) {
+ if (cs->halted) {
int64_t now = qemu_get_clock_ns(vm_clock);
xtensa_advance_ccount(env,
for (level = env->config->nlevel; level > minlevel; --level) {
if (env->config->level_mask[level] & int_set_enabled) {
env->pending_irq_level = level;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
qemu_log_mask(CPU_LOG_INT,
"%s level = %d, cintlevel = %d, "
"pc = %08x, a0 = %08x, ps = %08x, "
}
}
env->pending_irq_level = 0;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
static void xtensa_set_irq(void *opaque, int irq, int active)
{
XtensaCPU *cpu = opaque;
CPUXtensaState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
- if (env->halted) {
+ if (cs->halted) {
env->halt_clock = qemu_get_clock_ns(vm_clock);
xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]);
- if (!cpu_has_work(CPU(cpu))) {
+ if (!cpu_has_work(cs)) {
env->sregs[CCOUNT] = env->wake_ccount + 1;
xtensa_rearm_ccompare_timer(env);
}
| CPU_INTERRUPT_TGT_EXT_3 \
| CPU_INTERRUPT_TGT_EXT_4)
-#ifndef CONFIG_USER_ONLY
-typedef void (*CPUInterruptHandler)(CPUArchState *, int);
-
-extern CPUInterruptHandler cpu_interrupt_handler;
-
-static inline void cpu_interrupt(CPUArchState *s, int mask)
-{
- cpu_interrupt_handler(s, mask);
-}
-#else /* USER_ONLY */
-void cpu_interrupt(CPUArchState *env, int mask);
-#endif /* USER_ONLY */
-
-void cpu_reset_interrupt(CPUArchState *env, int mask);
-
void cpu_exit(CPUArchState *s);
/* Breakpoint/watchpoint flags */
accessed */ \
target_ulong mem_io_vaddr; /* target virtual addr at which the \
memory was accessed */ \
- uint32_t halted; /* Nonzero if the CPU is in suspend state */ \
- uint32_t interrupt_request; \
CPU_COMMON_TLB \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
/* buffer for temporaries in the code generator */ \
const VMStateSubsection *subsections;
};
+#ifdef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_dummy;
+#endif
+
extern const VMStateInfo vmstate_info_bool;
extern const VMStateInfo vmstate_info_int8;
void *opaque, int version_id);
void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
void *opaque);
-int vmstate_register(DeviceState *dev, int instance_id,
- const VMStateDescription *vmsd, void *base);
+
int vmstate_register_with_alias_id(DeviceState *dev, int instance_id,
const VMStateDescription *vmsd,
void *base, int alias_id,
int required_for_version);
+
+static inline int vmstate_register(DeviceState *dev, int instance_id,
+ const VMStateDescription *vmsd,
+ void *opaque)
+{
+ return vmstate_register_with_alias_id(dev, instance_id, vmsd,
+ opaque, -1, 0);
+}
+
void vmstate_unregister(DeviceState *dev, const VMStateDescription *vmsd,
void *opaque);
* @class_by_name: Callback to map -cpu command line model name to an
* instantiatable CPU type.
* @reset: Callback to reset the #CPUState to its initial state.
+ * @do_interrupt: Callback for interrupt handling.
+ * @vmsd: State description for migration.
*
* Represents a CPU family or model.
*/
ObjectClass *(*class_by_name)(const char *cpu_model);
void (*reset)(CPUState *cpu);
+ void (*do_interrupt)(CPUState *cpu);
+
+ const struct VMStateDescription *vmsd;
} CPUClass;
struct KVMState;
* @host_tid: Host thread ID.
* @running: #true if CPU is currently running (usermode).
* @created: Indicates whether the CPU thread has been successfully created.
+ * @interrupt_request: Indicates a pending interrupt request.
+ * @halted: Nonzero if the CPU is in suspended state.
* @stop: Indicates a pending stop request.
* @stopped: Indicates the CPU has been artificially stopped.
* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
bool stopped;
volatile sig_atomic_t exit_request;
volatile sig_atomic_t tcg_exit_req;
+ uint32_t interrupt_request;
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
/* TODO Move common fields from CPUArchState here. */
int cpu_index; /* used by alpha TCG */
+ uint32_t halted; /* used by alpha, cris, ppc TCG */
};
*/
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
+/**
+ * cpu_class_set_vmsd:
+ * @cc: CPU class
+ * @value: Value to set. Unused for %CONFIG_USER_ONLY.
+ *
+ * Sets #VMStateDescription for @cc.
+ *
+ * The @value argument is intentionally discarded for the non-softmmu targets
+ * to avoid linker errors or excessive preprocessor usage. If this behavior
+ * is undesired, you should assign #CPUState.vmsd directly instead.
+ */
+#ifndef CONFIG_USER_ONLY
+static inline void cpu_class_set_vmsd(CPUClass *cc,
+ const struct VMStateDescription *value)
+{
+ cc->vmsd = value;
+}
+#else
+#define cpu_class_set_vmsd(cc, value) ((cc)->vmsd = NULL)
+#endif
+
/**
* qemu_cpu_has_work:
* @cpu: The vCPU to check.
*/
CPUState *qemu_get_cpu(int index);
+#ifndef CONFIG_USER_ONLY
+
+typedef void (*CPUInterruptHandler)(CPUState *, int);
+
+extern CPUInterruptHandler cpu_interrupt_handler;
+
+/**
+ * cpu_interrupt:
+ * @cpu: The CPU to set an interrupt on.
+ * @mask: The interupts to set.
+ *
+ * Invokes the interrupt handler.
+ */
+static inline void cpu_interrupt(CPUState *cpu, int mask)
+{
+ cpu_interrupt_handler(cpu, mask);
+}
+
+#else /* USER_ONLY */
+
+void cpu_interrupt(CPUState *cpu, int mask);
+
+#endif /* USER_ONLY */
+
+/**
+ * cpu_reset_interrupt:
+ * @cpu: The CPU to clear the interrupt on.
+ * @mask: The interrupt mask to clear.
+ *
+ * Resets interrupts on the vCPU @cpu.
+ */
+void cpu_reset_interrupt(CPUState *cpu, int mask);
+
#endif
.priority = 10,
};
-static void kvm_handle_interrupt(CPUArchState *env, int mask)
+static void kvm_handle_interrupt(CPUState *cpu, int mask)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
- env->interrupt_request |= mask;
+ cpu->interrupt_request |= mask;
if (!qemu_cpu_is_self(cpu)) {
qemu_cpu_kick(cpu);
"Options and associated environment variables:\n"
"\n");
- maxarglen = maxenvlen = 0;
+ /* Calculate column widths. We must always have at least enough space
+ * for the column header.
+ */
+ maxarglen = strlen("Argument");
+ maxenvlen = strlen("Env-variable");
for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
+ int arglen = strlen(arginfo->argv);
+ if (arginfo->has_arg) {
+ arglen += strlen(arginfo->example) + 1;
+ }
if (strlen(arginfo->env) > maxenvlen) {
maxenvlen = strlen(arginfo->env);
}
- if (strlen(arginfo->argv) > maxarglen) {
- maxarglen = strlen(arginfo->argv);
+ if (arglen > maxarglen) {
+ maxarglen = arglen;
}
}
- printf("%-*s%-*sDescription\n", maxarglen+3, "Argument",
- maxenvlen+1, "Env-variable");
+ printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
+ maxenvlen, "Env-variable");
for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
if (arginfo->has_arg) {
printf("-%s %-*s %-*s %s\n", arginfo->argv,
- (int)(maxarglen-strlen(arginfo->argv)), arginfo->example,
- maxenvlen, arginfo->env, arginfo->help);
+ (int)(maxarglen - strlen(arginfo->argv) - 1),
+ arginfo->example, maxenvlen, arginfo->env, arginfo->help);
} else {
- printf("-%-*s %-*s %s\n", maxarglen+1, arginfo->argv,
+ printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
maxenvlen, arginfo->env,
arginfo->help);
}
#define TARGET_SOCK_MAX (SOCK_PACKET + 1)
+#elif defined(TARGET_ALPHA)
+
+ /* For setsockopt(2) */
+ #define TARGET_SOL_SOCKET 0xffff
+
+ #define TARGET_SO_DEBUG 0x0001
+ #define TARGET_SO_REUSEADDR 0x0004
+ #define TARGET_SO_KEEPALIVE 0x0008
+ #define TARGET_SO_DONTROUTE 0x0010
+ #define TARGET_SO_BROADCAST 0x0020
+ #define TARGET_SO_LINGER 0x0080
+ #define TARGET_SO_OOBINLINE 0x0100
+ /* To add :#define TARGET_SO_REUSEPORT 0x0200 */
+
+ #define TARGET_SO_TYPE 0x1008
+ #define TARGET_SO_ERROR 0x1007
+ #define TARGET_SO_SNDBUF 0x1001
+ #define TARGET_SO_RCVBUF 0x1002
+ #define TARGET_SO_SNDBUFFORCE 0x100a
+ #define TARGET_SO_RCVBUFFORCE 0x100b
+ #define TARGET_SO_RCVLOWAT 0x1010
+ #define TARGET_SO_SNDLOWAT 0x1011
+ #define TARGET_SO_RCVTIMEO 0x1012
+ #define TARGET_SO_SNDTIMEO 0x1013
+ #define TARGET_SO_ACCEPTCONN 0x1014
+ #define TARGET_SO_PROTOCOL 0x1028
+ #define TARGET_SO_DOMAIN 0x1029
+
+ /* linux-specific, might as well be the same as on i386 */
+ #define TARGET_SO_NO_CHECK 11
+ #define TARGET_SO_PRIORITY 12
+ #define TARGET_SO_BSDCOMPAT 14
+
+ #define TARGET_SO_PASSCRED 17
+ #define TARGET_SO_PEERCRED 18
+ #define TARGET_SO_BINDTODEVICE 25
+
+ /* Socket filtering */
+ #define TARGET_SO_ATTACH_FILTER 26
+ #define TARGET_SO_DETACH_FILTER 27
+
+ #define TARGET_SO_PEERNAME 28
+ #define TARGET_SO_TIMESTAMP 29
+ #define TARGET_SCM_TIMESTAMP TARGET_SO_TIMESTAMP
+
+ #define TARGET_SO_PEERSEC 30
+ #define TARGET_SO_PASSSEC 34
+ #define TARGET_SO_TIMESTAMPNS 35
+ #define TARGET_SCM_TIMESTAMPNS TARGET_SO_TIMESTAMPNS
+
+ /* Security levels - as per NRL IPv6 - don't actually do anything */
+ #define TARGET_SO_SECURITY_AUTHENTICATION 19
+ #define TARGET_SO_SECURITY_ENCRYPTION_TRANSPORT 20
+ #define TARGET_SO_SECURITY_ENCRYPTION_NETWORK 21
+
+ #define TARGET_SO_MARK 36
+
+ #define TARGET_SO_TIMESTAMPING 37
+ #define TARGET_SCM_TIMESTAMPING TARGET_SO_TIMESTAMPING
+
+ #define TARGET_SO_RXQ_OVFL 40
+
+ #define TARGET_SO_WIFI_STATUS 41
+ #define TARGET_SCM_WIFI_STATUS TARGET_SO_WIFI_STATUS
+ #define TARGET_SO_PEEK_OFF 42
+
+ /* Instruct lower device to use last 4-bytes of skb data as FCS */
+ #define TARGET_SO_NOFCS 43
+
#else
/* For setsockopt(2) */
#define TARGET_NR__newselect 230 /* Linux Specific */
#define TARGET_NR_time 231 /* Linux Specific */
#define TARGET_NR_stime 233 /* Linux Specific */
+#define TARGET_NR_statfs64 234 /* Linux Specific */
+#define TARGET_NR_fstatfs64 235 /* Linux Specific */
#define TARGET_NR__llseek 236 /* Linux Specific */
#define TARGET_NR_mlock 237
#define TARGET_NR_munlock 238
FLAG_END,
};
-UNUSED static struct flags fcntl_flags[] = {
- FLAG_TARGET(F_DUPFD),
- FLAG_TARGET(F_GETFD),
- FLAG_TARGET(F_SETFD),
- FLAG_TARGET(F_GETFL),
- FLAG_TARGET(F_SETFL),
- FLAG_TARGET(F_GETLK),
- FLAG_TARGET(F_SETLK),
- FLAG_TARGET(F_SETLKW),
- FLAG_END,
-};
-
UNUSED static struct flags clone_flags[] = {
FLAG_GENERIC(CLONE_VM),
FLAG_GENERIC(CLONE_FS),
{
print_syscall_prologue(name);
print_raw_param("%d", arg0, 0);
- print_flags(fcntl_flags, arg1, 0);
- /*
- * TODO: check flags and print following argument only
- * when needed.
- */
- print_pointer(arg2, 1);
+ switch(arg1) {
+ case TARGET_F_DUPFD:
+ gemu_log("F_DUPFD,");
+ print_raw_param(TARGET_ABI_FMT_ld, arg2, 1);
+ break;
+ case TARGET_F_GETFD:
+ gemu_log("F_GETFD");
+ break;
+ case TARGET_F_SETFD:
+ gemu_log("F_SETFD,");
+ print_raw_param(TARGET_ABI_FMT_ld, arg2, 1);
+ break;
+ case TARGET_F_GETFL:
+ gemu_log("F_GETFL");
+ break;
+ case TARGET_F_SETFL:
+ gemu_log("F_SETFL,");
+ print_open_flags(arg2, 1);
+ break;
+ case TARGET_F_GETLK:
+ gemu_log("F_GETLK,");
+ print_pointer(arg2, 1);
+ break;
+ case TARGET_F_SETLK:
+ gemu_log("F_SETLK,");
+ print_pointer(arg2, 1);
+ break;
+ case TARGET_F_SETLKW:
+ gemu_log("F_SETLKW,");
+ print_pointer(arg2, 1);
+ break;
+ case TARGET_F_GETOWN:
+ gemu_log("F_GETOWN");
+ break;
+ case TARGET_F_SETOWN:
+ gemu_log("F_SETOWN,");
+ print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
+ break;
+ case TARGET_F_GETSIG:
+ gemu_log("F_GETSIG");
+ break;
+ case TARGET_F_SETSIG:
+ gemu_log("F_SETSIG,");
+ print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
+ break;
+#if TARGET_ABI_BITS == 32
+ case TARGET_F_GETLK64:
+ gemu_log("F_GETLK64,");
+ print_pointer(arg2, 1);
+ break;
+ case TARGET_F_SETLK64:
+ gemu_log("F_SETLK64,");
+ print_pointer(arg2, 1);
+ break;
+ case TARGET_F_SETLKW64:
+ gemu_log("F_SETLKW64,");
+ print_pointer(arg2, 1);
+ break;
+#endif
+ case TARGET_F_SETLEASE:
+ gemu_log("F_SETLEASE,");
+ print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
+ break;
+ case TARGET_F_GETLEASE:
+ gemu_log("F_GETLEASE");
+ break;
+ case TARGET_F_DUPFD_CLOEXEC:
+ gemu_log("F_DUPFD_CLOEXEC,");
+ print_raw_param(TARGET_ABI_FMT_ld, arg2, 1);
+ break;
+ case TARGET_F_NOTIFY:
+ gemu_log("F_NOTIFY,");
+ print_raw_param(TARGET_ABI_FMT_ld, arg2, 0);
+ break;
+ default:
+ print_raw_param(TARGET_ABI_FMT_ld, arg1, 0);
+ print_pointer(arg2, 1);
+ break;
+ }
print_syscall_epilogue(name);
}
#define print_fcntl64 print_fcntl
gemu_log("FUTEX_PRIVATE_FLAG|");
cmd &= ~FUTEX_PRIVATE_FLAG;
}
+#endif
+#ifdef FUTEX_CLOCK_REALTIME
+ if (cmd & FUTEX_CLOCK_REALTIME) {
+ gemu_log("FUTEX_CLOCK_REALTIME|");
+ cmd &= ~FUTEX_CLOCK_REALTIME;
+ }
#endif
print_op(FUTEX_WAIT)
print_op(FUTEX_WAKE)
#ifdef CONFIG_ATTR
#include "qemu/xattr.h"
#endif
+#ifdef CONFIG_SENDFILE
+#include <sys/sendfile.h>
+#endif
#define termios host_termios
#define winsize host_winsize
errno = 0;
return NULL;
}
- if (count > IOV_MAX) {
+ if (count < 0 || count > IOV_MAX) {
errno = EINVAL;
return NULL;
}
return ret;
}
-/* do_accept() Must return target values and target errnos. */
-static abi_long do_accept(int fd, abi_ulong target_addr,
- abi_ulong target_addrlen_addr)
+/* If we don't have a system accept4() then just call accept.
+ * The callsites to do_accept4() will ensure that they don't
+ * pass a non-zero flags argument in this config.
+ */
+#ifndef CONFIG_ACCEPT4
+static inline int accept4(int sockfd, struct sockaddr *addr,
+ socklen_t *addrlen, int flags)
+{
+ assert(flags == 0);
+ return accept(sockfd, addr, addrlen);
+}
+#endif
+
+/* do_accept4() Must return target values and target errnos. */
+static abi_long do_accept4(int fd, abi_ulong target_addr,
+ abi_ulong target_addrlen_addr, int flags)
{
socklen_t addrlen;
void *addr;
abi_long ret;
- if (target_addr == 0)
- return get_errno(accept(fd, NULL, NULL));
+ if (target_addr == 0) {
+ return get_errno(accept4(fd, NULL, NULL, flags));
+ }
/* linux returns EINVAL if addrlen pointer is invalid */
if (get_user_u32(addrlen, target_addrlen_addr))
addr = alloca(addrlen);
- ret = get_errno(accept(fd, addr, &addrlen));
+ ret = get_errno(accept4(fd, addr, &addrlen, flags));
if (!is_error(ret)) {
host_to_target_sockaddr(target_addr, addr, addrlen);
if (put_user_u32(addrlen, target_addrlen_addr))
|| get_user_ual(target_addrlen, vptr + 2 * n))
return -TARGET_EFAULT;
- ret = do_accept(sockfd, target_addr, target_addrlen);
+ ret = do_accept4(sockfd, target_addr, target_addrlen, 0);
}
break;
case SOCKOP_getsockname:
#endif
switch (base_op) {
case FUTEX_WAIT:
+ case FUTEX_WAIT_BITSET:
if (timeout) {
pts = &ts;
target_to_host_timespec(pts, timeout);
pts = NULL;
}
return get_errno(sys_futex(g2h(uaddr), op, tswap32(val),
- pts, NULL, 0));
+ pts, NULL, val3));
case FUTEX_WAKE:
return get_errno(sys_futex(g2h(uaddr), op, val, NULL, NULL, 0));
case FUTEX_FD:
#endif
#ifdef TARGET_NR_accept
case TARGET_NR_accept:
- ret = do_accept(arg1, arg2, arg3);
+ ret = do_accept4(arg1, arg2, arg3, 0);
+ break;
+#endif
+#ifdef TARGET_NR_accept4
+ case TARGET_NR_accept4:
+#ifdef CONFIG_ACCEPT4
+ ret = do_accept4(arg1, arg2, arg3, arg4);
+#else
+ goto unimplemented;
+#endif
break;
#endif
#ifdef TARGET_NR_bind
#else
goto unimplemented;
#endif
+
+#ifdef CONFIG_SENDFILE
+ case TARGET_NR_sendfile:
+ {
+ off_t *offp = NULL;
+ off_t off;
+ if (arg3) {
+ ret = get_user_sal(off, arg3);
+ if (is_error(ret)) {
+ break;
+ }
+ offp = &off;
+ }
+ ret = get_errno(sendfile(arg1, arg2, offp, arg4));
+ if (!is_error(ret) && arg3) {
+ abi_long ret2 = put_user_sal(off, arg3);
+ if (is_error(ret2)) {
+ ret = ret2;
+ }
+ }
+ break;
+ }
+#ifdef TARGET_NR_sendfile64
+ case TARGET_NR_sendfile64:
+ {
+ off_t *offp = NULL;
+ off_t off;
+ if (arg3) {
+ ret = get_user_s64(off, arg3);
+ if (is_error(ret)) {
+ break;
+ }
+ offp = &off;
+ }
+ ret = get_errno(sendfile(arg1, arg2, offp, arg4));
+ if (!is_error(ret) && arg3) {
+ abi_long ret2 = put_user_s64(off, arg3);
+ if (is_error(ret2)) {
+ ret = ret2;
+ }
+ }
+ break;
+ }
+#endif
+#else
case TARGET_NR_sendfile:
+#ifdef TARGET_NR_sendfile64:
+ case TARGET_NR_sendfile64:
+#endif
goto unimplemented;
+#endif
+
#ifdef TARGET_NR_getpmsg
case TARGET_NR_getpmsg:
goto unimplemented;
{
int gidsetsize = arg1;
target_id *target_grouplist;
- gid_t *grouplist;
+ gid_t *grouplist = NULL;
int i;
-
- grouplist = alloca(gidsetsize * sizeof(gid_t));
- target_grouplist = lock_user(VERIFY_READ, arg2, gidsetsize * 2, 1);
- if (!target_grouplist) {
- ret = -TARGET_EFAULT;
- goto fail;
+ if (gidsetsize) {
+ grouplist = alloca(gidsetsize * sizeof(gid_t));
+ target_grouplist = lock_user(VERIFY_READ, arg2, gidsetsize * 2, 1);
+ if (!target_grouplist) {
+ ret = -TARGET_EFAULT;
+ goto fail;
+ }
+ for (i = 0; i < gidsetsize; i++) {
+ grouplist[i] = low2highgid(tswapid(target_grouplist[i]));
+ }
+ unlock_user(target_grouplist, arg2, 0);
}
- for(i = 0;i < gidsetsize; i++)
- grouplist[i] = low2highgid(tswapid(target_grouplist[i]));
- unlock_user(target_grouplist, arg2, 0);
ret = get_errno(setgroups(gidsetsize, grouplist));
}
break;
#ifdef TARGET_NR_set_robust_list
case TARGET_NR_set_robust_list:
- goto unimplemented_nowarn;
+ case TARGET_NR_get_robust_list:
+ /* The ABI for supporting robust futexes has userspace pass
+ * the kernel a pointer to a linked list which is updated by
+ * userspace after the syscall; the list is walked by the kernel
+ * when the thread exits. Since the linked list in QEMU guest
+ * memory isn't a valid linked list for the host and we have
+ * no way to reliably intercept the thread-death event, we can't
+ * support these. Silently return ENOSYS so that guest userspace
+ * falls back to a non-robust futex implementation (which should
+ * be OK except in the corner case of the guest crashing while
+ * holding a mutex that is shared with another process via
+ * shared memory).
+ */
+ goto unimplemented_nowarn;
#endif
#if defined(TARGET_NR_utimensat) && defined(__NR_utimensat)
/* set the current CPU defined by the user */
int monitor_set_cpu(int cpu_index)
{
- CPUArchState *env;
CPUState *cpu;
- for (env = first_cpu; env != NULL; env = env->next_cpu) {
- cpu = ENV_GET_CPU(env);
- if (cpu->cpu_index == cpu_index) {
- cur_mon->mon_cpu = env;
- return 0;
- }
+ cpu = qemu_get_cpu(cpu_index);
+ if (cpu == NULL) {
+ return -1;
}
- return -1;
+ cur_mon->mon_cpu = cpu->env_ptr;
+ return 0;
}
static CPUArchState *mon_get_cpu(void)
static gboolean ga_channel_open(GAChannel *c, GAChannelMethod method,
const gchar *path)
{
- if (!method == GA_CHANNEL_VIRTIO_SERIAL) {
+ if (method != GA_CHANNEL_VIRTIO_SERIAL) {
g_critical("unsupported communication method");
return false;
}
#include <sys/types.h>
#include <sys/ioctl.h>
#include <sys/wait.h>
+#include <unistd.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <inttypes.h>
#include "qga/guest-agent-core.h"
#include "qga-qmp-commands.h"
#include "qapi/qmp/qerror.h"
/* succeded */
}
+int64_t qmp_guest_get_time(Error **errp)
+{
+ int ret;
+ qemu_timeval tq;
+ int64_t time_ns;
+
+ ret = qemu_gettimeofday(&tq);
+ if (ret < 0) {
+ error_setg_errno(errp, errno, "Failed to get time");
+ return -1;
+ }
+
+ time_ns = tq.tv_sec * 1000000000LL + tq.tv_usec * 1000;
+ return time_ns;
+}
+
+void qmp_guest_set_time(int64_t time_ns, Error **errp)
+{
+ int ret;
+ int status;
+ pid_t pid;
+ Error *local_err = NULL;
+ struct timeval tv;
+
+ /* year-2038 will overflow in case time_t is 32bit */
+ if (time_ns / 1000000000 != (time_t)(time_ns / 1000000000)) {
+ error_setg(errp, "Time %" PRId64 " is too large", time_ns);
+ return;
+ }
+
+ tv.tv_sec = time_ns / 1000000000;
+ tv.tv_usec = (time_ns % 1000000000) / 1000;
+
+ ret = settimeofday(&tv, NULL);
+ if (ret < 0) {
+ error_setg_errno(errp, errno, "Failed to set time to guest");
+ return;
+ }
+
+ /* Set the Hardware Clock to the current System Time. */
+ pid = fork();
+ if (pid == 0) {
+ setsid();
+ reopen_fd_to_null(0);
+ reopen_fd_to_null(1);
+ reopen_fd_to_null(2);
+
+ execle("/sbin/hwclock", "hwclock", "-w", NULL, environ);
+ _exit(EXIT_FAILURE);
+ } else if (pid < 0) {
+ error_setg_errno(errp, errno, "failed to create child process");
+ return;
+ }
+
+ ga_wait_child(pid, &status, &local_err);
+ if (error_is_set(&local_err)) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (!WIFEXITED(status)) {
+ error_setg(errp, "child process has terminated abnormally");
+ return;
+ }
+
+ if (WEXITSTATUS(status)) {
+ error_setg(errp, "hwclock failed to set hardware clock to system time");
+ return;
+ }
+}
+
typedef struct GuestFileHandle {
uint64_t id;
FILE *fh;
QTAILQ_HEAD(, GuestFileHandle) filehandles;
} guest_file_state;
-static void guest_file_handle_add(FILE *fh)
+static int64_t guest_file_handle_add(FILE *fh, Error **errp)
{
GuestFileHandle *gfh;
+ int64_t handle;
+
+ handle = ga_get_fd_handle(ga_state, errp);
+ if (error_is_set(errp)) {
+ return 0;
+ }
gfh = g_malloc0(sizeof(GuestFileHandle));
- gfh->id = fileno(fh);
+ gfh->id = handle;
gfh->fh = fh;
QTAILQ_INSERT_TAIL(&guest_file_state.filehandles, gfh, next);
+
+ return handle;
}
static GuestFileHandle *guest_file_handle_find(int64_t id, Error **err)
{
FILE *fh;
int fd;
- int64_t ret = -1;
+ int64_t ret = -1, handle;
if (!has_mode) {
mode = "r";
return -1;
}
- guest_file_handle_add(fh);
- slog("guest-file-open, handle: %d", fd);
- return fd;
+ handle = guest_file_handle_add(fh, err);
+ if (error_is_set(err)) {
+ fclose(fh);
+ return -1;
+ }
+
+ slog("guest-file-open, handle: %d", handle);
+ return handle;
}
void qmp_guest_file_close(int64_t handle, Error **err)
return NULL;
}
+#define SYSCONF_EXACT(name, err) sysconf_exact((name), #name, (err))
+
+static long sysconf_exact(int name, const char *name_str, Error **err)
+{
+ long ret;
+
+ errno = 0;
+ ret = sysconf(name);
+ if (ret == -1) {
+ if (errno == 0) {
+ error_setg(err, "sysconf(%s): value indefinite", name_str);
+ } else {
+ error_setg_errno(err, errno, "sysconf(%s)", name_str);
+ }
+ }
+ return ret;
+}
+
+/* Transfer online/offline status between @vcpu and the guest system.
+ *
+ * On input either @errp or *@errp must be NULL.
+ *
+ * In system-to-@vcpu direction, the following @vcpu fields are accessed:
+ * - R: vcpu->logical_id
+ * - W: vcpu->online
+ * - W: vcpu->can_offline
+ *
+ * In @vcpu-to-system direction, the following @vcpu fields are accessed:
+ * - R: vcpu->logical_id
+ * - R: vcpu->online
+ *
+ * Written members remain unmodified on error.
+ */
+static void transfer_vcpu(GuestLogicalProcessor *vcpu, bool sys2vcpu,
+ Error **errp)
+{
+ char *dirpath;
+ int dirfd;
+
+ dirpath = g_strdup_printf("/sys/devices/system/cpu/cpu%" PRId64 "/",
+ vcpu->logical_id);
+ dirfd = open(dirpath, O_RDONLY | O_DIRECTORY);
+ if (dirfd == -1) {
+ error_setg_errno(errp, errno, "open(\"%s\")", dirpath);
+ } else {
+ static const char fn[] = "online";
+ int fd;
+ int res;
+
+ fd = openat(dirfd, fn, sys2vcpu ? O_RDONLY : O_RDWR);
+ if (fd == -1) {
+ if (errno != ENOENT) {
+ error_setg_errno(errp, errno, "open(\"%s/%s\")", dirpath, fn);
+ } else if (sys2vcpu) {
+ vcpu->online = true;
+ vcpu->can_offline = false;
+ } else if (!vcpu->online) {
+ error_setg(errp, "logical processor #%" PRId64 " can't be "
+ "offlined", vcpu->logical_id);
+ } /* otherwise pretend successful re-onlining */
+ } else {
+ unsigned char status;
+
+ res = pread(fd, &status, 1, 0);
+ if (res == -1) {
+ error_setg_errno(errp, errno, "pread(\"%s/%s\")", dirpath, fn);
+ } else if (res == 0) {
+ error_setg(errp, "pread(\"%s/%s\"): unexpected EOF", dirpath,
+ fn);
+ } else if (sys2vcpu) {
+ vcpu->online = (status != '0');
+ vcpu->can_offline = true;
+ } else if (vcpu->online != (status != '0')) {
+ status = '0' + vcpu->online;
+ if (pwrite(fd, &status, 1, 0) == -1) {
+ error_setg_errno(errp, errno, "pwrite(\"%s/%s\")", dirpath,
+ fn);
+ }
+ } /* otherwise pretend successful re-(on|off)-lining */
+
+ res = close(fd);
+ g_assert(res == 0);
+ }
+
+ res = close(dirfd);
+ g_assert(res == 0);
+ }
+
+ g_free(dirpath);
+}
+
+GuestLogicalProcessorList *qmp_guest_get_vcpus(Error **errp)
+{
+ int64_t current;
+ GuestLogicalProcessorList *head, **link;
+ long sc_max;
+ Error *local_err = NULL;
+
+ current = 0;
+ head = NULL;
+ link = &head;
+ sc_max = SYSCONF_EXACT(_SC_NPROCESSORS_CONF, &local_err);
+
+ while (local_err == NULL && current < sc_max) {
+ GuestLogicalProcessor *vcpu;
+ GuestLogicalProcessorList *entry;
+
+ vcpu = g_malloc0(sizeof *vcpu);
+ vcpu->logical_id = current++;
+ vcpu->has_can_offline = true; /* lolspeak ftw */
+ transfer_vcpu(vcpu, true, &local_err);
+
+ entry = g_malloc0(sizeof *entry);
+ entry->value = vcpu;
+
+ *link = entry;
+ link = &entry->next;
+ }
+
+ if (local_err == NULL) {
+ /* there's no guest with zero VCPUs */
+ g_assert(head != NULL);
+ return head;
+ }
+
+ qapi_free_GuestLogicalProcessorList(head);
+ error_propagate(errp, local_err);
+ return NULL;
+}
+
+int64_t qmp_guest_set_vcpus(GuestLogicalProcessorList *vcpus, Error **errp)
+{
+ int64_t processed;
+ Error *local_err = NULL;
+
+ processed = 0;
+ while (vcpus != NULL) {
+ transfer_vcpu(vcpus->value, false, &local_err);
+ if (local_err != NULL) {
+ break;
+ }
+ ++processed;
+ vcpus = vcpus->next;
+ }
+
+ if (local_err != NULL) {
+ if (processed == 0) {
+ error_propagate(errp, local_err);
+ } else {
+ error_free(local_err);
+ }
+ }
+
+ return processed;
+}
+
#else /* defined(__linux__) */
void qmp_guest_suspend_disk(Error **err)
return NULL;
}
+GuestLogicalProcessorList *qmp_guest_get_vcpus(Error **errp)
+{
+ error_set(errp, QERR_UNSUPPORTED);
+ return NULL;
+}
+
+int64_t qmp_guest_set_vcpus(GuestLogicalProcessorList *vcpus, Error **errp)
+{
+ error_set(errp, QERR_UNSUPPORTED);
+ return -1;
+}
+
#endif
#if !defined(CONFIG_FSFREEZE)
return NULL;
}
+int64_t qmp_guest_get_time(Error **errp)
+{
+ error_set(errp, QERR_UNSUPPORTED);
+ return -1;
+}
+
+void qmp_guest_set_time(int64_t time_ns, Error **errp)
+{
+ error_set(errp, QERR_UNSUPPORTED);
+}
+
+GuestLogicalProcessorList *qmp_guest_get_vcpus(Error **errp)
+{
+ error_set(errp, QERR_UNSUPPORTED);
+ return NULL;
+}
+
+int64_t qmp_guest_set_vcpus(GuestLogicalProcessorList *vcpus, Error **errp)
+{
+ error_set(errp, QERR_UNSUPPORTED);
+ return -1;
+}
+
/* register init/cleanup routines for stateful command groups */
void ga_command_state_init(GAState *s, GACommandState *cs)
{
void ga_set_frozen(GAState *s);
void ga_unset_frozen(GAState *s);
const char *ga_fsfreeze_hook(GAState *s);
+int64_t ga_get_fd_handle(GAState *s, Error **errp);
#ifndef _WIN32
void reopen_fd_to_null(int fd);
#include <stdbool.h>
#include <glib.h>
#include <getopt.h>
+#include <glib/gstdio.h>
#ifndef _WIN32
#include <syslog.h>
#include <sys/wait.h>
#include "qapi/qmp/qerror.h"
#include "qapi/qmp/dispatch.h"
#include "qga/channel.h"
+#include "qemu/bswap.h"
#ifdef _WIN32
#include "qga/service-win32.h"
#include <windows.h>
#endif
#define QGA_SENTINEL_BYTE 0xFF
+typedef struct GAPersistentState {
+#define QGA_PSTATE_DEFAULT_FD_COUNTER 1000
+ int64_t fd_counter;
+} GAPersistentState;
+
struct GAState {
JSONMessageParser parser;
GMainLoop *main_loop;
#ifdef CONFIG_FSFREEZE
const char *fsfreeze_hook;
#endif
+ const gchar *pstate_filepath;
+ GAPersistentState pstate;
};
struct GAState *ga_state;
"guest-ping",
"guest-info",
"guest-sync",
+ "guest-sync-delimited",
"guest-fsfreeze-status",
"guest-fsfreeze-thaw",
NULL
}
#endif
+static void set_persistent_state_defaults(GAPersistentState *pstate)
+{
+ g_assert(pstate);
+ pstate->fd_counter = QGA_PSTATE_DEFAULT_FD_COUNTER;
+}
+
+static void persistent_state_from_keyfile(GAPersistentState *pstate,
+ GKeyFile *keyfile)
+{
+ g_assert(pstate);
+ g_assert(keyfile);
+ /* if any fields are missing, either because the file was tampered with
+ * by agents of chaos, or because the field wasn't present at the time the
+ * file was created, the best we can ever do is start over with the default
+ * values. so load them now, and ignore any errors in accessing key-value
+ * pairs
+ */
+ set_persistent_state_defaults(pstate);
+
+ if (g_key_file_has_key(keyfile, "global", "fd_counter", NULL)) {
+ pstate->fd_counter =
+ g_key_file_get_int64(keyfile, "global", "fd_counter", NULL);
+ }
+}
+
+static void persistent_state_to_keyfile(const GAPersistentState *pstate,
+ GKeyFile *keyfile)
+{
+ g_assert(pstate);
+ g_assert(keyfile);
+
+ g_key_file_set_int64(keyfile, "global", "fd_counter", pstate->fd_counter);
+}
+
+static gboolean write_persistent_state(const GAPersistentState *pstate,
+ const gchar *path)
+{
+ GKeyFile *keyfile = g_key_file_new();
+ GError *gerr = NULL;
+ gboolean ret = true;
+ gchar *data = NULL;
+ gsize data_len;
+
+ g_assert(pstate);
+
+ persistent_state_to_keyfile(pstate, keyfile);
+ data = g_key_file_to_data(keyfile, &data_len, &gerr);
+ if (gerr) {
+ g_critical("failed to convert persistent state to string: %s",
+ gerr->message);
+ ret = false;
+ goto out;
+ }
+
+ g_file_set_contents(path, data, data_len, &gerr);
+ if (gerr) {
+ g_critical("failed to write persistent state to %s: %s",
+ path, gerr->message);
+ ret = false;
+ goto out;
+ }
+
+out:
+ if (gerr) {
+ g_error_free(gerr);
+ }
+ if (keyfile) {
+ g_key_file_free(keyfile);
+ }
+ g_free(data);
+ return ret;
+}
+
+static gboolean read_persistent_state(GAPersistentState *pstate,
+ const gchar *path, gboolean frozen)
+{
+ GKeyFile *keyfile = NULL;
+ GError *gerr = NULL;
+ struct stat st;
+ gboolean ret = true;
+
+ g_assert(pstate);
+
+ if (stat(path, &st) == -1) {
+ /* it's okay if state file doesn't exist, but any other error
+ * indicates a permissions issue or some other misconfiguration
+ * that we likely won't be able to recover from.
+ */
+ if (errno != ENOENT) {
+ g_critical("unable to access state file at path %s: %s",
+ path, strerror(errno));
+ ret = false;
+ goto out;
+ }
+
+ /* file doesn't exist. initialize state to default values and
+ * attempt to save now. (we could wait till later when we have
+ * modified state we need to commit, but if there's a problem,
+ * such as a missing parent directory, we want to catch it now)
+ *
+ * there is a potential scenario where someone either managed to
+ * update the agent from a version that didn't use a key store
+ * while qemu-ga thought the filesystem was frozen, or
+ * deleted the key store prior to issuing a fsfreeze, prior
+ * to restarting the agent. in this case we go ahead and defer
+ * initial creation till we actually have modified state to
+ * write, otherwise fail to recover from freeze.
+ */
+ set_persistent_state_defaults(pstate);
+ if (!frozen) {
+ ret = write_persistent_state(pstate, path);
+ if (!ret) {
+ g_critical("unable to create state file at path %s", path);
+ ret = false;
+ goto out;
+ }
+ }
+ ret = true;
+ goto out;
+ }
+
+ keyfile = g_key_file_new();
+ g_key_file_load_from_file(keyfile, path, 0, &gerr);
+ if (gerr) {
+ g_critical("error loading persistent state from path: %s, %s",
+ path, gerr->message);
+ ret = false;
+ goto out;
+ }
+
+ persistent_state_from_keyfile(pstate, keyfile);
+
+out:
+ if (keyfile) {
+ g_key_file_free(keyfile);
+ }
+ if (gerr) {
+ g_error_free(gerr);
+ }
+
+ return ret;
+}
+
+int64_t ga_get_fd_handle(GAState *s, Error **errp)
+{
+ int64_t handle;
+
+ g_assert(s->pstate_filepath);
+ /* we blacklist commands and avoid operations that potentially require
+ * writing to disk when we're in a frozen state. this includes opening
+ * new files, so we should never get here in that situation
+ */
+ g_assert(!ga_is_frozen(s));
+
+ handle = s->pstate.fd_counter++;
+ if (s->pstate.fd_counter < 0) {
+ s->pstate.fd_counter = 0;
+ }
+ if (!write_persistent_state(&s->pstate, s->pstate_filepath)) {
+ error_setg(errp, "failed to commit persistent state to disk");
+ }
+
+ return handle;
+}
+
int main(int argc, char **argv)
{
const char *sopt = "hVvdm:p:l:f:F::b:s:t:";
ga_enable_logging(s);
s->state_filepath_isfrozen = g_strdup_printf("%s/qga.state.isfrozen",
state_dir);
+ s->pstate_filepath = g_strdup_printf("%s/qga.state", state_dir);
s->frozen = false;
+
#ifndef _WIN32
/* check if a previous instance of qemu-ga exited with filesystems' state
* marked as frozen. this could be a stale value (a non-qemu-ga process
}
}
+ /* load persistent state from disk */
+ if (!read_persistent_state(&s->pstate,
+ s->pstate_filepath,
+ ga_is_frozen(s))) {
+ g_critical("failed to load persistent state");
+ goto out_bad;
+ }
+
if (blacklist) {
s->blacklist = blacklist;
do {
##
{ 'command': 'guest-ping' }
+##
+# @guest-get-time:
+#
+# Get the information about guest time relative to the Epoch
+# of 1970-01-01 in UTC.
+#
+# Returns: Time in nanoseconds.
+#
+# Since 1.5
+##
+{ 'command': 'guest-get-time',
+ 'returns': 'int' }
+
+##
+# @guest-set-time:
+#
+# Set guest time.
+#
+# When a guest is paused or migrated to a file then loaded
+# from that file, the guest OS has no idea that there
+# was a big gap in the time. Depending on how long the
+# gap was, NTP might not be able to resynchronize the
+# guest.
+#
+# This command tries to set guest time to the given value,
+# then sets the Hardware Clock to the current System Time.
+# This will make it easier for a guest to resynchronize
+# without waiting for NTP.
+#
+# @time: time of nanoseconds, relative to the Epoch of
+# 1970-01-01 in UTC.
+#
+# Returns: Nothing on success.
+#
+# Since: 1.5
+##
+{ 'command': 'guest-set-time',
+ 'data': { 'time': 'int' } }
+
##
# @GuestAgentCommandInfo:
#
##
{ 'command': 'guest-network-get-interfaces',
'returns': ['GuestNetworkInterface'] }
+
+##
+# @GuestLogicalProcessor:
+#
+# @logical-id: Arbitrary guest-specific unique identifier of the VCPU.
+#
+# @online: Whether the VCPU is enabled.
+#
+# @can-offline: Whether offlining the VCPU is possible. This member is always
+# filled in by the guest agent when the structure is returned,
+# and always ignored on input (hence it can be omitted then).
+#
+# Since: 1.5
+##
+{ 'type': 'GuestLogicalProcessor',
+ 'data': {'logical-id': 'int',
+ 'online': 'bool',
+ '*can-offline': 'bool'} }
+
+##
+# @guest-get-vcpus:
+#
+# Retrieve the list of the guest's logical processors.
+#
+# This is a read-only operation.
+#
+# Returns: The list of all VCPUs the guest knows about. Each VCPU is put on the
+# list exactly once, but their order is unspecified.
+#
+# Since: 1.5
+##
+{ 'command': 'guest-get-vcpus',
+ 'returns': ['GuestLogicalProcessor'] }
+
+##
+# @guest-set-vcpus:
+#
+# Attempt to reconfigure (currently: enable/disable) logical processors inside
+# the guest.
+#
+# The input list is processed node by node in order. In each node @logical-id
+# is used to look up the guest VCPU, for which @online specifies the requested
+# state. The set of distinct @logical-id's is only required to be a subset of
+# the guest-supported identifiers. There's no restriction on list length or on
+# repeating the same @logical-id (with possibly different @online field).
+# Preferably the input list should describe a modified subset of
+# @guest-get-vcpus' return value.
+#
+# Returns: The length of the initial sublist that has been successfully
+# processed. The guest agent maximizes this value. Possible cases:
+#
+# 0: if the @vcpus list was empty on input. Guest state
+# has not been changed. Otherwise,
+#
+# Error: processing the first node of @vcpus failed for the
+# reason returned. Guest state has not been changed.
+# Otherwise,
+#
+# < length(@vcpus): more than zero initial nodes have been processed,
+# but not the entire @vcpus list. Guest state has
+# changed accordingly. To retrieve the error
+# (assuming it persists), repeat the call with the
+# successfully processed initial sublist removed.
+# Otherwise,
+#
+# length(@vcpus): call successful.
+#
+# Since: 1.5
+##
+{ 'command': 'guest-set-vcpus',
+ 'data': {'vcpus': ['GuestLogicalProcessor'] },
+ 'returns': 'int' }
MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),
(char *)&message, 0,
NULL);
- n = printf("%s. (Error: %d) %s", text, err, message);
+ n = printf("%s. (Error: %d) %s", text, (int)err, message);
LocalFree(message);
return n;
#include "qom/cpu.h"
#include "qemu-common.h"
+void cpu_reset_interrupt(CPUState *cpu, int mask)
+{
+ cpu->interrupt_request &= ~mask;
+}
+
void cpu_reset(CPUState *cpu)
{
CPUClass *klass = CPU_GET_CLASS(cpu);
static void cpu_common_reset(CPUState *cpu)
{
cpu->exit_request = 0;
+ cpu->interrupt_request = 0;
cpu->current_tb = NULL;
+ cpu->halted = 0;
}
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
return 0;
}
-int vmstate_register(DeviceState *dev, int instance_id,
- const VMStateDescription *vmsd, void *opaque)
-{
- return vmstate_register_with_alias_id(dev, instance_id, vmsd,
- opaque, -1, 0);
-}
-
void vmstate_unregister(DeviceState *dev, const VMStateDescription *vmsd,
void *opaque)
{
#include "qemu-common.h"
#include "migration/vmstate.h"
+const VMStateDescription vmstate_dummy = {};
+
int vmstate_register_with_alias_id(DeviceState *dev,
int instance_id,
const VMStateDescription *vmsd,
#define ENV_OFFSET offsetof(AlphaCPU, env)
+void alpha_cpu_do_interrupt(CPUState *cpu);
+
#endif
dc->realize = alpha_cpu_realizefn;
cc->class_by_name = alpha_cpu_class_by_name;
+ cc->do_interrupt = alpha_cpu_do_interrupt;
}
static const TypeInfo alpha_cpu_type_info = {
int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
-void do_interrupt (CPUAlphaState *env);
void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUAlphaState *env = &ALPHA_CPU(cpu)->env;
-
/* Here we are checking to see if the CPU should wake up from HALT.
We will have gotten into this state only for WTINT from PALmode. */
/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
assume that if a CPU really wants to stay asleep, it will mask
interrupts at the chipset level, which will prevent these bits
from being set in the first place. */
- return env->interrupt_request & (CPU_INTERRUPT_HARD
+ return cpu->interrupt_request & (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
| CPU_INTERRUPT_SMP
| CPU_INTERRUPT_MCHK);
}
#endif /* USER_ONLY */
-void do_interrupt (CPUAlphaState *env)
+void alpha_cpu_do_interrupt(CPUState *cs)
{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
int i = env->exception_index;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
case 253:
/* WAIT */
tmp = tcg_const_i64(1);
- tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUAlphaState, halted));
+ tcg_gen_st32_i64(tmp, cpu_env, -offsetof(AlphaCPU, env) +
+ offsetof(CPUState, halted));
return gen_excp(ctx, EXCP_HLT, 0);
case 252:
void register_cp_regs_for_features(ARMCPU *cpu);
+void arm_cpu_do_interrupt(CPUState *cpu);
+void arm_v7m_cpu_do_interrupt(CPUState *cpu);
+
#endif
cpu->midr = 0x410fc231;
}
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
+{
+#ifndef CONFIG_USER_ONLY
+ CPUClass *cc = CPU_CLASS(oc);
+
+ cc->do_interrupt = arm_v7m_cpu_do_interrupt;
+#endif
+}
+
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
typedef struct ARMCPUInfo {
const char *name;
void (*initfn)(Object *obj);
+ void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo;
static const ARMCPUInfo arm_cpus[] = {
{ .name = "arm1136", .initfn = arm1136_initfn },
{ .name = "arm1176", .initfn = arm1176_initfn },
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
- { .name = "cortex-m3", .initfn = cortex_m3_initfn },
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
+ .class_init = arm_v7m_class_init },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
cc->reset = arm_cpu_reset;
cc->class_by_name = arm_cpu_class_by_name;
+ cc->do_interrupt = arm_cpu_do_interrupt;
}
static void cpu_register(const ARMCPUInfo *info)
.instance_size = sizeof(ARMCPU),
.instance_init = info->initfn,
.class_size = sizeof(ARMCPUClass),
+ .class_init = info->class_init,
};
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
void arm_translate_init(void);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
int cpu_arm_exec(CPUARMState *s);
-void do_interrupt(CPUARMState *);
int bank_number(int mode);
void switch_mode(CPUARMState *, int);
uint32_t do_arm_semihosting(CPUARMState *env);
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUARMState *env = &ARM_CPU(cpu)->env;
-
- return env->interrupt_request &
+ return cpu->interrupt_request &
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
uint64_t value)
{
/* Wait-for-interrupt (deprecated) */
- cpu_interrupt(env, CPU_INTERRUPT_HALT);
+ cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
return 0;
}
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUARMState *env)
+void arm_cpu_do_interrupt(CPUState *cs)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
env->exception_index = -1;
}
pointer. */
}
-static void do_interrupt_v7m(CPUARMState *env)
+void arm_v7m_cpu_do_interrupt(CPUState *cs)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
uint32_t xpsr = xpsr_read(env);
uint32_t lr;
uint32_t addr;
}
/* Handle a CPU exception. */
-void do_interrupt(CPUARMState *env)
+void arm_cpu_do_interrupt(CPUState *cs)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
uint32_t addr;
uint32_t mask;
int new_mode;
uint32_t offset;
- if (IS_M(env)) {
- do_interrupt_v7m(env);
- return;
- }
+ assert(!IS_M(env));
+
/* TODO: Vectored interrupt controller. */
switch (env->exception_index) {
case EXCP_UDEF:
}
env->regs[14] = env->regs[15] + offset;
env->regs[15] = addr;
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
/* Check section/page access permissions.
void HELPER(wfi)(CPUARMState *env)
{
+ CPUState *cs = CPU(arm_env_get_cpu(env));
+
env->exception_index = EXCP_HLT;
- env->halted = 1;
+ cs->halted = 1;
cpu_loop_exit(env);
}
#define ENV_OFFSET offsetof(CRISCPU, env)
+void cris_cpu_do_interrupt(CPUState *cpu);
+
#endif
cc->reset = cris_cpu_reset;
cc->class_by_name = cris_cpu_class_by_name;
+ cc->do_interrupt = cris_cpu_do_interrupt;
}
static const TypeInfo cris_cpu_type_info = {
CRISCPU *cpu_cris_init(const char *cpu_model);
int cpu_cris_exec(CPUCRISState *s);
-void do_interrupt(CPUCRISState *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUCRISState *env = &CRIS_CPU(cpu)->env;
-
- return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+ return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
#include "exec/exec-all.h"
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUCRISState *env)
+void cris_cpu_do_interrupt(CPUState *cs)
{
- env->exception_index = -1;
- env->pregs[PR_ERP] = env->pc;
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
+
+ env->exception_index = -1;
+ env->pregs[PR_ERP] = env->pc;
}
int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
int mmu_idx)
{
- env->exception_index = 0xaa;
- env->pregs[PR_EDA] = address;
- cpu_dump_state(env, stderr, fprintf, 0);
- return 1;
+ env->exception_index = 0xaa;
+ env->pregs[PR_EDA] = address;
+ cpu_dump_state(env, stderr, fprintf, 0);
+ return 1;
}
#else /* !CONFIG_USER_ONLY */
static void cris_shift_ccs(CPUCRISState *env)
{
- uint32_t ccs;
- /* Apply the ccs shift. */
- ccs = env->pregs[PR_CCS];
- ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
- env->pregs[PR_CCS] = ccs;
+ uint32_t ccs;
+ /* Apply the ccs shift. */
+ ccs = env->pregs[PR_CCS];
+ ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
+ env->pregs[PR_CCS] = ccs;
}
-int cpu_cris_handle_mmu_fault (CPUCRISState *env, target_ulong address, int rw,
- int mmu_idx)
+int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
+ int mmu_idx)
{
- struct cris_mmu_result res;
- int prot, miss;
- int r = -1;
- target_ulong phy;
-
- D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
- miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
- rw, mmu_idx, 0);
- if (miss)
- {
- if (env->exception_index == EXCP_BUSFAULT)
- cpu_abort(env,
- "CRIS: Illegal recursive bus fault."
- "addr=%x rw=%d\n",
- address, rw);
-
- env->pregs[PR_EDA] = address;
- env->exception_index = EXCP_BUSFAULT;
- env->fault_vector = res.bf_vec;
- r = 1;
- }
- else
- {
- /*
- * Mask off the cache selection bit. The ETRAX busses do not
- * see the top bit.
- */
- phy = res.phy & ~0x80000000;
- prot = res.prot;
- tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
- prot, mmu_idx, TARGET_PAGE_SIZE);
- r = 0;
- }
- if (r > 0)
- D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
- __func__, r, env->interrupt_request, address, res.phy,
- res.bf_vec, env->pc);
- return r;
+ D(CPUState *cpu = CPU(cris_env_get_cpu(env)));
+ struct cris_mmu_result res;
+ int prot, miss;
+ int r = -1;
+ target_ulong phy;
+
+ D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
+ miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
+ rw, mmu_idx, 0);
+ if (miss) {
+ if (env->exception_index == EXCP_BUSFAULT) {
+ cpu_abort(env,
+ "CRIS: Illegal recursive bus fault."
+ "addr=%x rw=%d\n",
+ address, rw);
+ }
+
+ env->pregs[PR_EDA] = address;
+ env->exception_index = EXCP_BUSFAULT;
+ env->fault_vector = res.bf_vec;
+ r = 1;
+ } else {
+ /*
+ * Mask off the cache selection bit. The ETRAX busses do not
+ * see the top bit.
+ */
+ phy = res.phy & ~0x80000000;
+ prot = res.prot;
+ tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
+ prot, mmu_idx, TARGET_PAGE_SIZE);
+ r = 0;
+ }
+ if (r > 0) {
+ D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
+ __func__, r, cpu->interrupt_request, address, res.phy,
+ res.bf_vec, env->pc);
+ }
+ return r;
}
static void do_interruptv10(CPUCRISState *env)
{
- int ex_vec = -1;
-
- D_LOG( "exception index=%d interrupt_req=%d\n",
- env->exception_index,
- env->interrupt_request);
-
- assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
- switch (env->exception_index)
- {
- case EXCP_BREAK:
- /* These exceptions are genereated by the core itself.
- ERP should point to the insn following the brk. */
- ex_vec = env->trap_vector;
- env->pregs[PRV10_BRP] = env->pc;
- break;
-
- case EXCP_NMI:
- /* NMI is hardwired to vector zero. */
- ex_vec = 0;
- env->pregs[PR_CCS] &= ~M_FLAG_V10;
- env->pregs[PRV10_BRP] = env->pc;
- break;
-
- case EXCP_BUSFAULT:
- cpu_abort(env, "Unhandled busfault");
- break;
-
- default:
- /* The interrupt controller gives us the vector. */
- ex_vec = env->interrupt_vector;
- /* Normal interrupts are taken between
- TB's. env->pc is valid here. */
- env->pregs[PR_ERP] = env->pc;
- break;
- }
-
- if (env->pregs[PR_CCS] & U_FLAG) {
- /* Swap stack pointers. */
- env->pregs[PR_USP] = env->regs[R_SP];
- env->regs[R_SP] = env->ksp;
- }
-
- /* Now that we are in kernel mode, load the handlers address. */
- env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
- env->locked_irq = 1;
- env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
-
- qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
- __func__, env->pc, ex_vec,
- env->pregs[PR_CCS],
- env->pregs[PR_PID],
- env->pregs[PR_ERP]);
+ D(CPUState *cs = CPU(cris_env_get_cpu(env)));
+ int ex_vec = -1;
+
+ D_LOG("exception index=%d interrupt_req=%d\n",
+ env->exception_index,
+ cs->interrupt_request);
+
+ assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
+ switch (env->exception_index) {
+ case EXCP_BREAK:
+ /* These exceptions are genereated by the core itself.
+ ERP should point to the insn following the brk. */
+ ex_vec = env->trap_vector;
+ env->pregs[PRV10_BRP] = env->pc;
+ break;
+
+ case EXCP_NMI:
+ /* NMI is hardwired to vector zero. */
+ ex_vec = 0;
+ env->pregs[PR_CCS] &= ~M_FLAG_V10;
+ env->pregs[PRV10_BRP] = env->pc;
+ break;
+
+ case EXCP_BUSFAULT:
+ cpu_abort(env, "Unhandled busfault");
+ break;
+
+ default:
+ /* The interrupt controller gives us the vector. */
+ ex_vec = env->interrupt_vector;
+ /* Normal interrupts are taken between
+ TB's. env->pc is valid here. */
+ env->pregs[PR_ERP] = env->pc;
+ break;
+ }
+
+ if (env->pregs[PR_CCS] & U_FLAG) {
+ /* Swap stack pointers. */
+ env->pregs[PR_USP] = env->regs[R_SP];
+ env->regs[R_SP] = env->ksp;
+ }
+
+ /* Now that we are in kernel mode, load the handlers address. */
+ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
+ env->locked_irq = 1;
+ env->pregs[PR_CCS] |= F_FLAG_V10; /* set F. */
+
+ qemu_log_mask(CPU_LOG_INT, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
+ __func__, env->pc, ex_vec,
+ env->pregs[PR_CCS],
+ env->pregs[PR_PID],
+ env->pregs[PR_ERP]);
}
-void do_interrupt(CPUCRISState *env)
+void cris_cpu_do_interrupt(CPUState *cs)
{
- int ex_vec = -1;
-
- if (env->pregs[PR_VR] < 32)
- return do_interruptv10(env);
-
- D_LOG( "exception index=%d interrupt_req=%d\n",
- env->exception_index,
- env->interrupt_request);
-
- switch (env->exception_index)
- {
- case EXCP_BREAK:
- /* These exceptions are genereated by the core itself.
- ERP should point to the insn following the brk. */
- ex_vec = env->trap_vector;
- env->pregs[PR_ERP] = env->pc;
- break;
-
- case EXCP_NMI:
- /* NMI is hardwired to vector zero. */
- ex_vec = 0;
- env->pregs[PR_CCS] &= ~M_FLAG_V32;
- env->pregs[PR_NRP] = env->pc;
- break;
-
- case EXCP_BUSFAULT:
- ex_vec = env->fault_vector;
- env->pregs[PR_ERP] = env->pc;
- break;
-
- default:
- /* The interrupt controller gives us the vector. */
- ex_vec = env->interrupt_vector;
- /* Normal interrupts are taken between
- TB's. env->pc is valid here. */
- env->pregs[PR_ERP] = env->pc;
- break;
- }
-
- /* Fill in the IDX field. */
- env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
-
- if (env->dslot) {
- D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
- " ERP=%x pid=%x ccs=%x cc=%d %x\n",
- ex_vec, env->pc, env->dslot,
- env->regs[R_SP],
- env->pregs[PR_ERP], env->pregs[PR_PID],
- env->pregs[PR_CCS],
- env->cc_op, env->cc_mask);
- /* We loose the btarget, btaken state here so rexec the
- branch. */
- env->pregs[PR_ERP] -= env->dslot;
- /* Exception starts with dslot cleared. */
- env->dslot = 0;
- }
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
+ int ex_vec = -1;
+
+ if (env->pregs[PR_VR] < 32) {
+ return do_interruptv10(env);
+ }
+
+ D_LOG("exception index=%d interrupt_req=%d\n",
+ env->exception_index,
+ cs->interrupt_request);
+
+ switch (env->exception_index) {
+ case EXCP_BREAK:
+ /* These exceptions are genereated by the core itself.
+ ERP should point to the insn following the brk. */
+ ex_vec = env->trap_vector;
+ env->pregs[PR_ERP] = env->pc;
+ break;
+
+ case EXCP_NMI:
+ /* NMI is hardwired to vector zero. */
+ ex_vec = 0;
+ env->pregs[PR_CCS] &= ~M_FLAG_V32;
+ env->pregs[PR_NRP] = env->pc;
+ break;
+
+ case EXCP_BUSFAULT:
+ ex_vec = env->fault_vector;
+ env->pregs[PR_ERP] = env->pc;
+ break;
+
+ default:
+ /* The interrupt controller gives us the vector. */
+ ex_vec = env->interrupt_vector;
+ /* Normal interrupts are taken between
+ TB's. env->pc is valid here. */
+ env->pregs[PR_ERP] = env->pc;
+ break;
+ }
+
+ /* Fill in the IDX field. */
+ env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
+
+ if (env->dslot) {
+ D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
+ " ERP=%x pid=%x ccs=%x cc=%d %x\n",
+ ex_vec, env->pc, env->dslot,
+ env->regs[R_SP],
+ env->pregs[PR_ERP], env->pregs[PR_PID],
+ env->pregs[PR_CCS],
+ env->cc_op, env->cc_mask);
+ /* We loose the btarget, btaken state here so rexec the
+ branch. */
+ env->pregs[PR_ERP] -= env->dslot;
+ /* Exception starts with dslot cleared. */
+ env->dslot = 0;
+ }
- if (env->pregs[PR_CCS] & U_FLAG) {
- /* Swap stack pointers. */
- env->pregs[PR_USP] = env->regs[R_SP];
- env->regs[R_SP] = env->ksp;
- }
-
- /* Apply the CRIS CCS shift. Clears U if set. */
- cris_shift_ccs(env);
-
- /* Now that we are in kernel mode, load the handlers address.
- This load may not fault, real hw leaves that behaviour as
- undefined. */
- env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
-
- /* Clear the excption_index to avoid spurios hw_aborts for recursive
- bus faults. */
- env->exception_index = -1;
-
- D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
- __func__, env->pc, ex_vec,
- env->pregs[PR_CCS],
- env->pregs[PR_PID],
- env->pregs[PR_ERP]);
+ if (env->pregs[PR_CCS] & U_FLAG) {
+ /* Swap stack pointers. */
+ env->pregs[PR_USP] = env->regs[R_SP];
+ env->regs[R_SP] = env->ksp;
+ }
+
+ /* Apply the CRIS CCS shift. Clears U if set. */
+ cris_shift_ccs(env);
+
+ /* Now that we are in kernel mode, load the handlers address.
+ This load may not fault, real hw leaves that behaviour as
+ undefined. */
+ env->pc = cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4);
+
+ /* Clear the excption_index to avoid spurios hw_aborts for recursive
+ bus faults. */
+ env->exception_index = -1;
+
+ D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
+ __func__, env->pc, ex_vec,
+ env->pregs[PR_CCS],
+ env->pregs[PR_PID],
+ env->pregs[PR_ERP]);
}
hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
{
- uint32_t phy = addr;
- struct cris_mmu_result res;
- int miss;
-
- miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
- /* If D TLB misses, try I TLB. */
- if (miss) {
- miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
- }
-
- if (!miss)
- phy = res.phy;
- D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
- return phy;
+ uint32_t phy = addr;
+ struct cris_mmu_result res;
+ int miss;
+
+ miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
+ /* If D TLB misses, try I TLB. */
+ if (miss) {
+ miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
+ }
+
+ if (!miss) {
+ phy = res.phy;
+ }
+ D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));
+ return phy;
}
#endif
cris_cc_mask(dc, 0);
if (dc->op2 == 15) {
- t_gen_mov_env_TN(halted, tcg_const_tl(1));
+ tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
+ -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
tcg_gen_movi_tl(env_pc, dc->pc + 2);
t_gen_raise_exception(EXCP_HLT);
return 2;
#define ENV_OFFSET offsetof(X86CPU, env)
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_x86_cpu;
+#endif
+
+/**
+ * x86_cpu_do_interrupt:
+ * @cpu: vCPU the interrupt is to be handled by.
+ */
+void x86_cpu_do_interrupt(CPUState *cpu);
+
#endif
apic_designate_bsp(env->apic_state);
}
- env->halted = !cpu_is_bsp(cpu);
+ s->halted = !cpu_is_bsp(cpu);
#endif
}
xcc->parent_reset = cc->reset;
cc->reset = x86_cpu_reset;
+
+ cc->do_interrupt = x86_cpu_do_interrupt;
+ cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
}
static const TypeInfo x86_cpu_type_info = {
static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
int sipi_vector)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
env->eip = 0;
sipi_vector << 12,
env->segs[R_CS].limit,
env->segs[R_CS].flags);
- env->halted = 0;
+ cs->halted = 0;
}
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
#define cpu_list x86_cpu_list
#define cpudef_setup x86_cpudef_setup
-#define CPU_SAVE_VERSION 12
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#include "hw/apic.h"
#endif
-static inline bool cpu_has_work(CPUState *cpu)
+static inline bool cpu_has_work(CPUState *cs)
{
- CPUX86State *env = &X86_CPU(cpu)->env;
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
- return ((env->interrupt_request & (CPU_INTERRUPT_HARD |
- CPU_INTERRUPT_POLL)) &&
+ return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
+ CPU_INTERRUPT_POLL)) &&
(env->eflags & IF_MASK)) ||
- (env->interrupt_request & (CPU_INTERRUPT_NMI |
- CPU_INTERRUPT_INIT |
- CPU_INTERRUPT_SIPI |
- CPU_INTERRUPT_MCE));
+ (cs->interrupt_request & (CPU_INTERRUPT_NMI |
+ CPU_INTERRUPT_INIT |
+ CPU_INTERRUPT_SIPI |
+ CPU_INTERRUPT_MCE));
}
#include "exec/exec-all.h"
uint64_t param);
void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
-/* op_helper.c */
-void do_interrupt(CPUX86State *env);
+/* seg_helper.c */
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
void do_smm_enter(CPUX86State *env1);
void cpu_dump_state(CPUX86State *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
int eflags, i, nb;
char cc_op_name[32];
static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
- env->halted);
+ cs->halted);
} else
#endif
{
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
- env->halted);
+ cs->halted);
}
for(i = 0; i < 6; i++) {
#endif
/* if the cpu is currently executing code, we must unlink it and
all the potentially executing TB */
- cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_EXITTB);
/* when a20 is changed, all the MMU mappings are invalid, so
we must flush everything */
banks[3] = params->misc;
cenv->mcg_status = params->mcg_status;
banks[1] = params->status;
- cpu_interrupt(cenv, CPU_INTERRUPT_MCE);
+ cpu_interrupt(cpu, CPU_INTERRUPT_MCE);
} else if (!(banks[1] & MCI_STATUS_VAL)
|| !(banks[1] & MCI_STATUS_UC)) {
if (banks[1] & MCI_STATUS_VAL) {
if (kvm_enabled()) {
env->tpr_access_type = access;
- cpu_interrupt(env, CPU_INTERRUPT_TPR);
+ cpu_interrupt(CPU(x86_env_get_cpu(env)), CPU_INTERRUPT_TPR);
} else {
cpu_restore_state(env, env->mem_io_pc);
#if !defined(CONFIG_USER_ONLY)
void do_cpu_init(X86CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
- int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI;
+ int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI;
uint64_t pat = env->pat;
- cpu_reset(CPU(cpu));
- env->interrupt_request = sipi;
+ cpu_reset(cs);
+ cs->interrupt_request = sipi;
env->pat = pat;
apic_init_reset(env->apic_state);
}
static int kvm_get_mp_state(X86CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
struct kvm_mp_state mp_state;
int ret;
- ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state);
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
if (ret < 0) {
return ret;
}
env->mp_state = mp_state.mp_state;
if (kvm_irqchip_in_kernel()) {
- env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
+ cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
}
return 0;
}
int ret;
/* Inject NMI */
- if (env->interrupt_request & CPU_INTERRUPT_NMI) {
- env->interrupt_request &= ~CPU_INTERRUPT_NMI;
+ if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
+ cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
DPRINTF("injected NMI\n");
ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
if (ret < 0) {
if (!kvm_irqchip_in_kernel()) {
/* Force the VCPU out of its inner loop to process any INIT requests
* or pending TPR access reports. */
- if (env->interrupt_request &
+ if (cpu->interrupt_request &
(CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
cpu->exit_request = 1;
}
/* Try to inject an interrupt if the guest can accept it */
if (run->ready_for_interrupt_injection &&
- (env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) {
int irq;
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
irq = cpu_get_pic_interrupt(env);
if (irq >= 0) {
struct kvm_interrupt intr;
* interrupt, request an interrupt window exit. This will
* cause a return to userspace as soon as the guest is ready to
* receive interrupts. */
- if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
+ if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
run->request_interrupt_window = 1;
} else {
run->request_interrupt_window = 0;
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
- if (env->interrupt_request & CPU_INTERRUPT_MCE) {
+ if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
/* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
assert(env->mcg_cap);
- env->interrupt_request &= ~CPU_INTERRUPT_MCE;
+ cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
kvm_cpu_synchronize_state(env);
env->exception_injected = EXCP12_MCHK;
env->has_error_code = 0;
- env->halted = 0;
+ cs->halted = 0;
if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
env->mp_state = KVM_MP_STATE_RUNNABLE;
}
return 0;
}
- if (env->interrupt_request & CPU_INTERRUPT_POLL) {
- env->interrupt_request &= ~CPU_INTERRUPT_POLL;
+ if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
+ cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
apic_poll_irq(env->apic_state);
}
- if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) ||
- (env->interrupt_request & CPU_INTERRUPT_NMI)) {
- env->halted = 0;
+ (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
+ cs->halted = 0;
}
- if (env->interrupt_request & CPU_INTERRUPT_INIT) {
+ if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
kvm_cpu_synchronize_state(env);
do_cpu_init(cpu);
}
- if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
+ if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
kvm_cpu_synchronize_state(env);
do_cpu_sipi(cpu);
}
- if (env->interrupt_request & CPU_INTERRUPT_TPR) {
- env->interrupt_request &= ~CPU_INTERRUPT_TPR;
+ if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
+ cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
kvm_cpu_synchronize_state(env);
apic_handle_tpr_access_report(env->apic_state, env->eip,
env->tpr_access_type);
}
- return env->halted;
+ return cs->halted;
}
static int kvm_handle_halt(X86CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
- if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) &&
- !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
- env->halted = 1;
+ !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
+ cs->halted = 1;
return EXCP_HLT;
}
static bool fpregs_is_0(void *opaque, int version_id)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
return (env->fpregs_format_vmstate == 0);
}
static bool fpregs_is_1_mmx(void *opaque, int version_id)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
int guess_mmx;
guess_mmx = ((env->fptag_vmstate == 0xff) &&
static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
int guess_mmx;
guess_mmx = ((env->fptag_vmstate == 0xff) &&
static void cpu_pre_save(void *opaque)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
int i;
/* FPU */
static int cpu_post_load(void *opaque, int version_id)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
int i;
/* XXX: restore FPU round state */
static bool async_pf_msr_needed(void *opaque)
{
- CPUX86State *cpu = opaque;
+ X86CPU *cpu = opaque;
- return cpu->async_pf_en_msr != 0;
+ return cpu->env.async_pf_en_msr != 0;
}
static bool pv_eoi_msr_needed(void *opaque)
{
- CPUX86State *cpu = opaque;
+ X86CPU *cpu = opaque;
- return cpu->pv_eoi_en_msr != 0;
+ return cpu->env.pv_eoi_en_msr != 0;
}
static const VMStateDescription vmstate_async_pf_msr = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT64(async_pf_en_msr, CPUX86State),
+ VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
VMSTATE_END_OF_LIST()
}
};
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT64(pv_eoi_en_msr, CPUX86State),
+ VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
VMSTATE_END_OF_LIST()
}
};
static bool fpop_ip_dp_needed(void *opaque)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
}
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT16(fpop, CPUX86State),
- VMSTATE_UINT64(fpip, CPUX86State),
- VMSTATE_UINT64(fpdp, CPUX86State),
+ VMSTATE_UINT16(env.fpop, X86CPU),
+ VMSTATE_UINT64(env.fpip, X86CPU),
+ VMSTATE_UINT64(env.fpdp, X86CPU),
VMSTATE_END_OF_LIST()
}
};
static bool tsc_adjust_needed(void *opaque)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
return env->tsc_adjust != 0;
}
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
- VMSTATE_UINT64(tsc_adjust, CPUX86State),
+ VMSTATE_UINT64(env.tsc_adjust, X86CPU),
VMSTATE_END_OF_LIST()
}
};
static bool tscdeadline_needed(void *opaque)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
return env->tsc_deadline != 0;
}
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT64(tsc_deadline, CPUX86State),
+ VMSTATE_UINT64(env.tsc_deadline, X86CPU),
VMSTATE_END_OF_LIST()
}
};
static bool misc_enable_needed(void *opaque)
{
- CPUX86State *env = opaque;
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
}
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField []) {
- VMSTATE_UINT64(msr_ia32_misc_enable, CPUX86State),
+ VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
VMSTATE_END_OF_LIST()
}
};
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
- .version_id = CPU_SAVE_VERSION,
+ .version_id = 12,
.minimum_version_id = 3,
.minimum_version_id_old = 3,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField []) {
- VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),
- VMSTATE_UINTTL(eip, CPUX86State),
- VMSTATE_UINTTL(eflags, CPUX86State),
- VMSTATE_UINT32(hflags, CPUX86State),
+ VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
+ VMSTATE_UINTTL(env.eip, X86CPU),
+ VMSTATE_UINTTL(env.eflags, X86CPU),
+ VMSTATE_UINT32(env.hflags, X86CPU),
/* FPU */
- VMSTATE_UINT16(fpuc, CPUX86State),
- VMSTATE_UINT16(fpus_vmstate, CPUX86State),
- VMSTATE_UINT16(fptag_vmstate, CPUX86State),
- VMSTATE_UINT16(fpregs_format_vmstate, CPUX86State),
- VMSTATE_FP_REGS(fpregs, CPUX86State, 8),
-
- VMSTATE_SEGMENT_ARRAY(segs, CPUX86State, 6),
- VMSTATE_SEGMENT(ldt, CPUX86State),
- VMSTATE_SEGMENT(tr, CPUX86State),
- VMSTATE_SEGMENT(gdt, CPUX86State),
- VMSTATE_SEGMENT(idt, CPUX86State),
-
- VMSTATE_UINT32(sysenter_cs, CPUX86State),
+ VMSTATE_UINT16(env.fpuc, X86CPU),
+ VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
+ VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
+ VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
+ VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
+
+ VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
+ VMSTATE_SEGMENT(env.ldt, X86CPU),
+ VMSTATE_SEGMENT(env.tr, X86CPU),
+ VMSTATE_SEGMENT(env.gdt, X86CPU),
+ VMSTATE_SEGMENT(env.idt, X86CPU),
+
+ VMSTATE_UINT32(env.sysenter_cs, X86CPU),
#ifdef TARGET_X86_64
/* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
- VMSTATE_HACK_UINT32(sysenter_esp, CPUX86State, less_than_7),
- VMSTATE_HACK_UINT32(sysenter_eip, CPUX86State, less_than_7),
- VMSTATE_UINTTL_V(sysenter_esp, CPUX86State, 7),
- VMSTATE_UINTTL_V(sysenter_eip, CPUX86State, 7),
+ VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
+ VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
+ VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
+ VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
#else
- VMSTATE_UINTTL(sysenter_esp, CPUX86State),
- VMSTATE_UINTTL(sysenter_eip, CPUX86State),
+ VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
+ VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
#endif
- VMSTATE_UINTTL(cr[0], CPUX86State),
- VMSTATE_UINTTL(cr[2], CPUX86State),
- VMSTATE_UINTTL(cr[3], CPUX86State),
- VMSTATE_UINTTL(cr[4], CPUX86State),
- VMSTATE_UINTTL_ARRAY(dr, CPUX86State, 8),
+ VMSTATE_UINTTL(env.cr[0], X86CPU),
+ VMSTATE_UINTTL(env.cr[2], X86CPU),
+ VMSTATE_UINTTL(env.cr[3], X86CPU),
+ VMSTATE_UINTTL(env.cr[4], X86CPU),
+ VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
/* MMU */
- VMSTATE_INT32(a20_mask, CPUX86State),
+ VMSTATE_INT32(env.a20_mask, X86CPU),
/* XMM */
- VMSTATE_UINT32(mxcsr, CPUX86State),
- VMSTATE_XMM_REGS(xmm_regs, CPUX86State, CPU_NB_REGS),
+ VMSTATE_UINT32(env.mxcsr, X86CPU),
+ VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS),
#ifdef TARGET_X86_64
- VMSTATE_UINT64(efer, CPUX86State),
- VMSTATE_UINT64(star, CPUX86State),
- VMSTATE_UINT64(lstar, CPUX86State),
- VMSTATE_UINT64(cstar, CPUX86State),
- VMSTATE_UINT64(fmask, CPUX86State),
- VMSTATE_UINT64(kernelgsbase, CPUX86State),
+ VMSTATE_UINT64(env.efer, X86CPU),
+ VMSTATE_UINT64(env.star, X86CPU),
+ VMSTATE_UINT64(env.lstar, X86CPU),
+ VMSTATE_UINT64(env.cstar, X86CPU),
+ VMSTATE_UINT64(env.fmask, X86CPU),
+ VMSTATE_UINT64(env.kernelgsbase, X86CPU),
#endif
- VMSTATE_UINT32_V(smbase, CPUX86State, 4),
-
- VMSTATE_UINT64_V(pat, CPUX86State, 5),
- VMSTATE_UINT32_V(hflags2, CPUX86State, 5),
-
- VMSTATE_UINT32_TEST(halted, CPUX86State, version_is_5),
- VMSTATE_UINT64_V(vm_hsave, CPUX86State, 5),
- VMSTATE_UINT64_V(vm_vmcb, CPUX86State, 5),
- VMSTATE_UINT64_V(tsc_offset, CPUX86State, 5),
- VMSTATE_UINT64_V(intercept, CPUX86State, 5),
- VMSTATE_UINT16_V(intercept_cr_read, CPUX86State, 5),
- VMSTATE_UINT16_V(intercept_cr_write, CPUX86State, 5),
- VMSTATE_UINT16_V(intercept_dr_read, CPUX86State, 5),
- VMSTATE_UINT16_V(intercept_dr_write, CPUX86State, 5),
- VMSTATE_UINT32_V(intercept_exceptions, CPUX86State, 5),
- VMSTATE_UINT8_V(v_tpr, CPUX86State, 5),
+ VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
+
+ VMSTATE_UINT64_V(env.pat, X86CPU, 5),
+ VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
+
+ VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5),
+ VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
+ VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
+ VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
+ VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
+ VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
+ VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
+ VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
+ VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
+ VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
+ VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
/* MTRRs */
- VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUX86State, 11, 8),
- VMSTATE_UINT64_V(mtrr_deftype, CPUX86State, 8),
- VMSTATE_MTRR_VARS(mtrr_var, CPUX86State, 8, 8),
+ VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
+ VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
+ VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8),
/* KVM-related states */
- VMSTATE_INT32_V(interrupt_injected, CPUX86State, 9),
- VMSTATE_UINT32_V(mp_state, CPUX86State, 9),
- VMSTATE_UINT64_V(tsc, CPUX86State, 9),
- VMSTATE_INT32_V(exception_injected, CPUX86State, 11),
- VMSTATE_UINT8_V(soft_interrupt, CPUX86State, 11),
- VMSTATE_UINT8_V(nmi_injected, CPUX86State, 11),
- VMSTATE_UINT8_V(nmi_pending, CPUX86State, 11),
- VMSTATE_UINT8_V(has_error_code, CPUX86State, 11),
- VMSTATE_UINT32_V(sipi_vector, CPUX86State, 11),
+ VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
+ VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
+ VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
+ VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
+ VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
+ VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
+ VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
+ VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
+ VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
/* MCE */
- VMSTATE_UINT64_V(mcg_cap, CPUX86State, 10),
- VMSTATE_UINT64_V(mcg_status, CPUX86State, 10),
- VMSTATE_UINT64_V(mcg_ctl, CPUX86State, 10),
- VMSTATE_UINT64_ARRAY_V(mce_banks, CPUX86State, MCE_BANKS_DEF *4, 10),
+ VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
+ VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
+ VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
+ VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
/* rdtscp */
- VMSTATE_UINT64_V(tsc_aux, CPUX86State, 11),
+ VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
/* KVM pvclock msr */
- VMSTATE_UINT64_V(system_time_msr, CPUX86State, 11),
- VMSTATE_UINT64_V(wall_clock_msr, CPUX86State, 11),
+ VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
+ VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
/* XSAVE related fields */
- VMSTATE_UINT64_V(xcr0, CPUX86State, 12),
- VMSTATE_UINT64_V(xstate_bv, CPUX86State, 12),
- VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUX86State, CPU_NB_REGS, 12),
+ VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
+ VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
+ VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
VMSTATE_END_OF_LIST()
/* The above list is not sorted /wrt version numbers, watch out! */
},
}
}
};
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
}
#endif
-static void do_hlt(CPUX86State *env)
+static void do_hlt(X86CPU *cpu)
{
+ CPUState *cs = CPU(cpu);
+ CPUX86State *env = &cpu->env;
+
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
- env->halted = 1;
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
void helper_hlt(CPUX86State *env, int next_eip_addend)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
+
cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
EIP += next_eip_addend;
- do_hlt(env);
+ do_hlt(cpu);
}
void helper_monitor(CPUX86State *env, target_ulong ptr)
void helper_mwait(CPUX86State *env, int next_eip_addend)
{
- CPUState *cpu;
+ CPUState *cs;
+ X86CPU *cpu;
if ((uint32_t)ECX != 0) {
raise_exception(env, EXCP0D_GPF);
cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
EIP += next_eip_addend;
- cpu = CPU(x86_env_get_cpu(env));
+ cpu = x86_env_get_cpu(env);
+ cs = CPU(cpu);
/* XXX: not complete but not completely erroneous */
- if (cpu->cpu_index != 0 || env->next_cpu != NULL) {
+ if (cs->cpu_index != 0 || env->next_cpu != NULL) {
/* more than one CPU: do not sleep because another CPU may
wake this one */
} else {
- do_hlt(env);
+ do_hlt(cpu);
}
}
#endif
}
-void do_interrupt(CPUX86State *env)
+void x86_cpu_do_interrupt(CPUState *cs)
{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
#if defined(CONFIG_USER_ONLY)
/* if user mode only, we simulate a fake exception
which will be handled outside the cpu execution
env->hflags2 |= HF2_GIF_MASK;
if (int_ctl & V_IRQ_MASK) {
- env->interrupt_request |= CPU_INTERRUPT_VIRQ;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+
+ cs->interrupt_request |= CPU_INTERRUPT_VIRQ;
}
/* maybe we need to inject an event */
/* Note: currently only 32 bits of exit_code are used */
void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
uint32_t int_ctl;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmexit(%08x, %016" PRIx64 ", %016"
int_ctl = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
int_ctl &= ~(V_TPR_MASK | V_IRQ_MASK);
int_ctl |= env->v_tpr & V_TPR_MASK;
- if (env->interrupt_request & CPU_INTERRUPT_VIRQ) {
+ if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
int_ctl |= V_IRQ_MASK;
}
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl);
env->hflags &= ~HF_SVMI_MASK;
env->intercept = 0;
env->intercept_exceptions = 0;
- env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
+ cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
env->tsc_offset = 0;
env->gdt.base = ldq_phys(env->vm_hsave + offsetof(struct vmcb,
#define ENV_OFFSET offsetof(LM32CPU, env)
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_lm32_cpu;
+#endif
+
+void lm32_cpu_do_interrupt(CPUState *cpu);
+
#endif
lcc->parent_reset = cc->reset;
cc->reset = lm32_cpu_reset;
+
+ cc->do_interrupt = lm32_cpu_do_interrupt;
+ cpu_class_set_vmsd(cc, &vmstate_lm32_cpu);
}
static const TypeInfo lm32_cpu_type_info = {
LM32CPU *cpu_lm32_init(const char *cpu_model);
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_lm32_exec(CPULM32State *s);
-void do_interrupt(CPULM32State *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
#define cpu_gen_code cpu_lm32_gen_code
#define cpu_signal_handler cpu_lm32_signal_handler
-#define CPU_SAVE_VERSION 1
-
int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
static inline bool cpu_has_work(CPUState *cpu)
{
- CPULM32State *env = &LM32_CPU(cpu)->env;
-
- return env->interrupt_request & CPU_INTERRUPT_HARD;
+ return cpu->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec/exec-all.h"
return addr & TARGET_PAGE_MASK;
}
-void do_interrupt(CPULM32State *env)
+void lm32_cpu_do_interrupt(CPUState *cs)
{
+ LM32CPU *cpu = LM32_CPU(cs);
+ CPULM32State *env = &cpu->env;
+
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%x type=%x\n", env->pc, env->exception_index);
#include "hw/hw.h"
#include "hw/boards.h"
-static const VMStateDescription vmstate_cpu = {
- .name = "cpu",
- .version_id = CPU_SAVE_VERSION,
+static const VMStateDescription vmstate_env = {
+ .name = "env",
+ .version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
}
};
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
+const VMStateDescription vmstate_lm32_cpu = {
+ .name = "cpu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(env, LM32CPU, 1, vmstate_env, CPULM32State),
+ VMSTATE_END_OF_LIST()
+ }
+};
void helper_hlt(CPULM32State *env)
{
- env->halted = 1;
+ CPUState *cs = CPU(lm32_env_get_cpu(env));
+
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
#define ENV_OFFSET offsetof(M68kCPU, env)
+void m68k_cpu_do_interrupt(CPUState *cpu);
+
#endif
cc->reset = m68k_cpu_reset;
cc->class_by_name = m68k_cpu_class_by_name;
+ cc->do_interrupt = m68k_cpu_do_interrupt;
dc->vmsd = &vmstate_m68k_cpu;
}
void m68k_cpu_init_gdb(M68kCPU *cpu);
M68kCPU *cpu_m68k_init(const char *cpu_model);
int cpu_m68k_exec(CPUM68KState *s);
-void do_interrupt(CPUM68KState *env1);
void do_interrupt_m68k_hardirq(CPUM68KState *env1);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUM68KState *env = &M68K_CPU(cpu)->env;
-
- return env->interrupt_request & CPU_INTERRUPT_HARD;
+ return cpu->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec/exec-all.h"
simplicitly we calculate it when the interrupt is signalled. */
void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)
{
+ CPUState *cs = CPU(cpu);
CPUM68KState *env = &cpu->env;
env->pending_level = level;
env->pending_vector = vector;
- if (level)
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
- else
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ if (level) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
}
#endif
#if defined(CONFIG_USER_ONLY)
-void do_interrupt(CPUM68KState *env)
+void m68k_cpu_do_interrupt(CPUState *cs)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
env->exception_index = -1;
}
static void do_interrupt_all(CPUM68KState *env, int is_hw)
{
+ CPUState *cs;
uint32_t sp;
uint32_t fmt;
uint32_t retaddr;
do_m68k_semihosting(env, env->dregs[0]);
return;
}
- env->halted = 1;
+ cs = CPU(m68k_env_get_cpu(env));
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit(env);
return;
env->pc = cpu_ldl_kernel(env, env->vbr + vector);
}
-void do_interrupt(CPUM68KState *env)
+void m68k_cpu_do_interrupt(CPUState *cs)
{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
do_interrupt_all(env, 0);
}
DEFO32(DIV1, div1)
DEFO32(DIV2, div2)
DEFO32(EXCEPTION, exception_index)
-DEFO32(HALTED, halted)
DEFO32(MACSR, macsr)
DEFO32(MAC_MASK, mac_mask)
#undef DEFO64
#undef DEFF64
+static TCGv_i32 cpu_halted;
+
static TCGv_ptr cpu_env;
static char cpu_reg_names[3*8*3 + 5*4];
#undef DEFO64
#undef DEFF64
+ cpu_halted = tcg_global_mem_new_i32(TCG_AREG0,
+ -offsetof(M68kCPU, env) +
+ offsetof(CPUState, halted), "HALTED");
+
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
p = cpu_reg_names;
s->pc += 2;
gen_set_sr_im(s, ext, 0);
- tcg_gen_movi_i32(QREG_HALTED, 1);
+ tcg_gen_movi_i32(cpu_halted, 1);
gen_exception(s, s->pc, EXCP_HLT);
}
#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
+void mb_cpu_do_interrupt(CPUState *cs);
+
#endif
mcc->parent_reset = cc->reset;
cc->reset = mb_cpu_reset;
+ cc->do_interrupt = mb_cpu_do_interrupt;
dc->vmsd = &vmstate_mb_cpu;
}
void mb_tcg_init(void);
MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
int cpu_mb_exec(CPUMBState *s);
-void do_interrupt(CPUMBState *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUMBState *env = &MICROBLAZE_CPU(cpu)->env;
-
- return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+ return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
#include "exec/exec-all.h"
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUMBState *env)
+void mb_cpu_do_interrupt(CPUState *cs)
{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
+
env->exception_index = -1;
env->res_addr = RES_ADDR_NONE;
env->regs[14] = env->sregs[SR_PC];
return r;
}
-void do_interrupt(CPUMBState *env)
+void mb_cpu_do_interrupt(CPUState *cs)
{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
uint32_t t;
/* IMM flag cannot propagate across a branch and into the dslot. */
#define ENV_OFFSET offsetof(MIPSCPU, env)
+void mips_cpu_do_interrupt(CPUState *cpu);
+
#endif
mcc->parent_reset = cc->reset;
cc->reset = mips_cpu_reset;
+
+ cc->do_interrupt = mips_cpu_do_interrupt;
}
static const TypeInfo mips_cpu_type_info = {
int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
-void do_interrupt (CPUMIPSState *env);
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
/* It is implementation dependent if non-enabled interrupts
wake-up the CPU, however most of the implementations only
check for interrupts that can be taken. */
- if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
has_work = true;
}
if (env->CP0_Config3 & (1 << CP0C3_MT)) {
/* The QEMU model will issue an _WAKE request whenever the CPUs
should be woken up. */
- if (env->interrupt_request & CPU_INTERRUPT_WAKE) {
+ if (cpu->interrupt_request & CPU_INTERRUPT_WAKE) {
has_work = true;
}
}
#endif
-void do_interrupt (CPUMIPSState *env)
+void mips_cpu_do_interrupt(CPUState *cs)
{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
#if !defined(CONFIG_USER_ONLY)
- MIPSCPU *cpu = mips_env_get_cpu(env);
target_ulong offset;
int cause = -1;
const char *name;
/* SMP helpers. */
static bool mips_vpe_is_wfi(MIPSCPU *c)
{
+ CPUState *cpu = CPU(c);
CPUMIPSState *env = &c->env;
/* If the VPE is halted but otherwise active, it means it's waiting for
an interrupt. */
- return env->halted && mips_vpe_active(env);
+ return cpu->halted && mips_vpe_active(env);
}
-static inline void mips_vpe_wake(CPUMIPSState *c)
+static inline void mips_vpe_wake(MIPSCPU *c)
{
/* Dont set ->halted = 0 directly, let it be done via cpu_has_work
because there might be other conditions that state that c should
be sleeping. */
- cpu_interrupt(c, CPU_INTERRUPT_WAKE);
+ cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
}
static inline void mips_vpe_sleep(MIPSCPU *cpu)
{
- CPUMIPSState *c = &cpu->env;
+ CPUState *cs = CPU(cpu);
/* The VPE was shut off, really go to bed.
Reset any old _WAKE requests. */
- c->halted = 1;
- cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
+ cs->halted = 1;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
}
static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
/* FIXME: TC reschedule. */
if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
- mips_vpe_wake(c);
+ mips_vpe_wake(cpu);
}
}
&& !mips_vpe_is_wfi(other_cpu)) {
/* Enable the VPE. */
other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
- mips_vpe_wake(other_cpu_env); /* And wake it up. */
+ mips_vpe_wake(other_cpu); /* And wake it up. */
}
other_cpu_env = other_cpu_env->next_cpu;
} while (other_cpu_env);
void helper_wait(CPUMIPSState *env)
{
- env->halted = 1;
- cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
+ CPUState *cs = CPU(mips_env_get_cpu(env));
+
+ cs->halted = 1;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
helper_raise_exception(env, EXCP_HLT);
}
env->tcs[i].CP0_TCHalt = 1;
}
env->active_tc.CP0_TCHalt = 1;
- env->halted = 1;
+ cs->halted = 1;
if (cs->cpu_index == 0) {
/* VPE0 starts up enabled. */
env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
/* TC0 starts up unhalted. */
- env->halted = 0;
+ cs->halted = 0;
env->active_tc.CP0_TCHalt = 0;
env->tcs[0].CP0_TCHalt = 0;
/* With thread 0 active. */
cc->reset = openrisc_cpu_reset;
cc->class_by_name = openrisc_cpu_class_by_name;
+ cc->do_interrupt = openrisc_cpu_do_interrupt;
}
static void cpu_register(const OpenRISCCPUInfo *info)
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_openrisc_exec(CPUOpenRISCState *s);
-void do_interrupt(CPUOpenRISCState *env);
+void openrisc_cpu_do_interrupt(CPUState *cpu);
void openrisc_translate_init(void);
int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
target_ulong address,
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUOpenRISCState *env = &OPENRISC_CPU(cpu)->env;
-
- return env->interrupt_request & (CPU_INTERRUPT_HARD |
+ return cpu->interrupt_request & (CPU_INTERRUPT_HARD |
CPU_INTERRUPT_TIMER);
}
#include "hw/loader.h"
#endif
-void do_interrupt(CPUOpenRISCState *env)
+void openrisc_cpu_do_interrupt(CPUState *cs)
{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ CPUOpenRISCState *env = &cpu->env;
#ifndef CONFIG_USER_ONLY
if (env->flags & D_FLAG) { /* Delay Slot insn */
env->flags &= ~D_FLAG;
void HELPER(rfe)(CPUOpenRISCState *env)
{
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
#ifndef CONFIG_USER_ONLY
int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
(cpu->env.esr & (SR_SM | SR_IME | SR_DME));
tlb_flush(&cpu->env, 1);
}
#endif
- cpu->env.interrupt_request |= CPU_INTERRUPT_EXITTB;
+ cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
int idx;
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
switch (spr) {
case TO_SPR(0, 0): /* VR */
env->ttmr = (rb & ~TTMR_IP) + ip;
} else { /* Clear IP bit. */
env->ttmr = rb & ~TTMR_IP;
- env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
+ cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
}
cpu_openrisc_count_update(cpu);
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
+void ppc_cpu_do_interrupt(CPUState *cpu);
+
#endif
int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
-void do_interrupt (CPUPPCState *env);
void ppc_hw_interrupt (CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUPPCState *env = &POWERPC_CPU(cpu)->env;
+ PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);
+ CPUPPCState *env = &ppc_cpu->env;
- return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
+ return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD);
}
#include "exec/exec-all.h"
/*****************************************************************************/
/* Exception processing */
#if defined(CONFIG_USER_ONLY)
-void do_interrupt(CPUPPCState *env)
+void ppc_cpu_do_interrupt(CPUState *cs)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
env->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
}
static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
{
CPUPPCState *env = &cpu->env;
+ CPUState *cs;
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
int lpes0, lpes1, lev;
fprintf(stderr, "Machine check while not allowed. "
"Entering checkstop state\n");
}
- env->halted = 1;
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ cs = CPU(cpu);
+ cs->halted = 1;
+ cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
if (0) {
/* XXX: find a suitable condition to enable the hypervisor mode */
}
}
-void do_interrupt(CPUPPCState *env)
+void ppc_cpu_do_interrupt(CPUState *cs)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
powerpc_excp(cpu, env->excp_model, env->exception_index);
}
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
int hdice;
-
#if 0
+ CPUState *cs = CPU(cpu);
+
qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
- __func__, env, env->pending_interrupts,
- env->interrupt_request, (int)msr_me, (int)msr_ee);
+ __func__, env, env->pending_interrupts,
+ cs->interrupt_request, (int)msr_me, (int)msr_ee);
#endif
/* External reset */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
#if !defined(CONFIG_USER_ONLY)
void helper_store_msr(CPUPPCState *env, target_ulong val)
{
+ CPUState *cs;
+
val = hreg_store_msr(env, val, 0);
if (val != 0) {
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ cs = CPU(ppc_env_get_cpu(env));
+ cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
helper_raise_exception(env, val);
}
}
static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr,
target_ulong msrm, int keep_msrh)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
#if defined(TARGET_PPC64)
if (msr_is_64bit(env, msr)) {
nip = (uint64_t)nip;
/* No need to raise an exception here,
* as rfi is always the last insn of a TB
*/
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
void helper_rfi(CPUPPCState *env)
for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
cenv->pending_interrupts |= 1 << irq;
- cpu_interrupt(cenv, CPU_INTERRUPT_HARD);
+ cpu_interrupt(CPU(ppc_env_get_cpu(cenv)), CPU_INTERRUPT_HARD);
}
}
}
int alter_hv)
{
int excp;
+#if !defined(CONFIG_USER_ONLY)
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+#endif
excp = 0;
value &= env->msr_mask;
-#if !defined (CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
if (!alter_hv) {
/* mtmsr cannot alter the hypervisor state */
value &= ~MSR_HVB;
/* Flush all tlb when changing translation mode */
tlb_flush(env, 1);
excp = POWERPC_EXCP_NONE;
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
((value ^ env->msr) & (1 << MSR_TGPR)))) {
#endif
env->msr = value;
hreg_compute_hflags(env);
-#if !defined (CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
if (unlikely(msr_pow == 1)) {
if ((*env->check_pow)(env)) {
- env->halted = 1;
+ cs->halted = 1;
excp = EXCP_HALTED;
}
}
* interrupt, reset, etc) in PPC-specific env->irq_input_state. */
if (!cap_interrupt_level &&
run->ready_for_interrupt_injection &&
- (env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->irq_input_state & (1<<PPC_INPUT_INT)))
{
/* For now KVM disregards the 'irq' argument. However, in the
int kvm_arch_process_async_events(CPUState *cs)
{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- return cpu->env.halted;
+ return cs->halted;
}
-static int kvmppc_handle_halt(CPUPPCState *env)
+static int kvmppc_handle_halt(PowerPCCPU *cpu)
{
- if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
- env->halted = 1;
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+
+ if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
}
break;
case KVM_EXIT_HLT:
dprintf("handle halt\n");
- ret = kvmppc_handle_halt(env);
+ ret = kvmppc_handle_halt(cpu);
break;
#ifdef CONFIG_PSERIES
case KVM_EXIT_PAPR_HCALL:
static void gen_wait(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
+ tcg_gen_st_i32(t0, cpu_env,
+ -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
tcg_temp_free_i32(t0);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_err(ctx, EXCP_HLT, 1);
cc->reset = ppc_cpu_reset;
cc->class_by_name = ppc_cpu_class_by_name;
+ cc->do_interrupt = ppc_cpu_do_interrupt;
}
static const TypeInfo ppc_cpu_type_info = {
#define ENV_OFFSET offsetof(S390CPU, env)
+void s390_cpu_do_interrupt(CPUState *cpu);
+
#endif
env->cregs[0] = CR0_RESET;
env->cregs[14] = CR14_RESET;
/* set halted to 1 to make sure we can add the cpu in
- * s390_ipl_cpu code, where env->halted is set back to 0
+ * s390_ipl_cpu code, where CPUState::halted is set back to 0
* after incrementing the cpu counter */
#if !defined(CONFIG_USER_ONLY)
- env->halted = 1;
+ s->halted = 1;
#endif
tlb_flush(env, 1);
}
env->tod_basetime = 0;
env->tod_timer = qemu_new_timer_ns(vm_clock, s390x_tod_timer, cpu);
env->cpu_timer = qemu_new_timer_ns(vm_clock, s390x_cpu_timer, cpu);
- /* set env->halted state to 1 to avoid decrementing the running
+ /* set CPUState::halted state to 1 to avoid decrementing the running
* cpu counter in s390_cpu_reset to a negative number at
* initial ipl */
- env->halted = 1;
+ cs->halted = 1;
#endif
env->cpu_num = cpu_num++;
env->ext_index = -1;
scc->parent_reset = cc->reset;
cc->reset = s390_cpu_reset;
+ cc->do_interrupt = s390_cpu_do_interrupt;
dc->vmsd = &vmstate_s390_cpu;
}
S390CPU *cpu_s390x_init(const char *cpu_model);
void s390x_translate_init(void);
int cpu_s390x_exec(CPUS390XState *s);
-void do_interrupt (CPUS390XState *env);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
env->ext_queue[env->ext_index].param64 = param64;
env->pending_int |= INTERRUPT_EXT;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
env->io_queue[env->io_index[isc]][isc].word = io_int_word;
env->pending_int |= INTERRUPT_IO;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
static inline void cpu_inject_crw_mchk(S390CPU *cpu)
env->mchk_queue[env->mchk_index].type = 1;
env->pending_int |= INTERRUPT_MCHK;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUS390XState *env = &S390_CPU(cpu)->env;
+ S390CPU *s390_cpu = S390_CPU(cpu);
+ CPUS390XState *env = &s390_cpu->env;
- return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->psw.mask & PSW_MASK_EXT);
}
CPUS390XState *env = &cpu->env;
env->pending_int |= INTERRUPT_TOD;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
void s390x_cpu_timer(void *opaque)
CPUS390XState *env = &cpu->env;
env->pending_int |= INTERRUPT_CPUTIMER;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
#endif
#if defined(CONFIG_USER_ONLY)
-void do_interrupt(CPUS390XState *env)
+void s390_cpu_do_interrupt(CPUState *cs)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
env->exception_index = -1;
}
{
if (mask & PSW_MASK_WAIT) {
S390CPU *cpu = s390_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
if (s390_del_running_cpu(cpu) == 0) {
#ifndef CONFIG_USER_ONLY
#endif
}
}
- env->halted = 1;
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
}
load_psw(env, mask, addr);
}
-void do_interrupt(CPUS390XState *env)
+void s390_cpu_do_interrupt(CPUState *cs)
{
- S390CPU *cpu = s390_env_get_cpu(env);
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
__func__, env->exception_index, env->psw.addr);
env->exception_index = -1;
if (!env->pending_int) {
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
}
}
#define TYPE_SUPERH_CPU "superh-cpu"
+#define TYPE_SH7750R_CPU "sh7750r-" TYPE_SUPERH_CPU
+#define TYPE_SH7751R_CPU "sh7751r-" TYPE_SUPERH_CPU
+#define TYPE_SH7785_CPU "sh7785-" TYPE_SUPERH_CPU
+
#define SUPERH_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
#define SUPERH_CPU(obj) \
* SuperHCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
+ * @name: The name.
+ * @pvr: Processor Version Register
+ * @prr: Processor Revision Register
+ * @cvr: Cache Version Register
*
* A SuperH CPU model.
*/
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
+
+ const char *name;
+ uint32_t pvr;
+ uint32_t prr;
+ uint32_t cvr;
} SuperHCPUClass;
/**
#define ENV_OFFSET offsetof(SuperHCPU, env)
+void superh_cpu_do_interrupt(CPUState *cpu);
+
#endif
set_default_nan_mode(1, &env->fp_status);
}
+typedef struct SuperHCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} SuperHCPUListState;
+
+/* Sort alphabetically by type name. */
+static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+ const char *name_a, *name_b;
+
+ name_a = object_class_get_name(class_a);
+ name_b = object_class_get_name(class_b);
+ return strcmp(name_a, name_b);
+}
+
+static void superh_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+ SuperHCPUListState *s = user_data;
+
+ (*s->cpu_fprintf)(s->file, "%s\n",
+ scc->name);
+}
+
+void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ SuperHCPUListState s = {
+ .cpu_fprintf = cpu_fprintf,
+ .file = f,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_SUPERH_CPU, false);
+ list = g_slist_sort(list, superh_cpu_list_compare);
+ g_slist_foreach(list, superh_cpu_list_entry, &s);
+ g_slist_free(list);
+}
+
+static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
+{
+ const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
+ const char *name = b;
+
+ return strcasecmp(scc->name, name);
+}
+
+static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
+{
+ ObjectClass *oc;
+ GSList *list, *item;
+
+ if (cpu_model == NULL) {
+ return NULL;
+ }
+ if (strcasecmp(cpu_model, "any") == 0) {
+ return object_class_by_name(TYPE_SH7750R_CPU);
+ }
+
+ oc = object_class_by_name(cpu_model);
+ if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
+ && !object_class_is_abstract(oc)) {
+ return oc;
+ }
+
+ oc = NULL;
+ list = object_class_get_list(TYPE_SUPERH_CPU, false);
+ item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
+ if (item != NULL) {
+ oc = item->data;
+ }
+ g_slist_free(list);
+ return oc;
+}
+
+SuperHCPU *cpu_sh4_init(const char *cpu_model)
+{
+ SuperHCPU *cpu;
+ CPUSH4State *env;
+ ObjectClass *oc;
+
+ oc = superh_cpu_class_by_name(cpu_model);
+ if (oc == NULL) {
+ return NULL;
+ }
+ cpu = SUPERH_CPU(object_new(object_class_get_name(oc)));
+ env = &cpu->env;
+ env->cpu_model_str = cpu_model;
+
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
+ return cpu;
+}
+
+static void sh7750r_cpu_initfn(Object *obj)
+{
+ SuperHCPU *cpu = SUPERH_CPU(obj);
+ CPUSH4State *env = &cpu->env;
+
+ env->id = SH_CPU_SH7750R;
+ env->features = SH_FEATURE_BCR3_AND_BCR4;
+}
+
+static void sh7750r_class_init(ObjectClass *oc, void *data)
+{
+ SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+ scc->name = "SH7750R";
+ scc->pvr = 0x00050000;
+ scc->prr = 0x00000100;
+ scc->cvr = 0x00110000;
+}
+
+static const TypeInfo sh7750r_type_info = {
+ .name = TYPE_SH7750R_CPU,
+ .parent = TYPE_SUPERH_CPU,
+ .class_init = sh7750r_class_init,
+ .instance_init = sh7750r_cpu_initfn,
+};
+
+static void sh7751r_cpu_initfn(Object *obj)
+{
+ SuperHCPU *cpu = SUPERH_CPU(obj);
+ CPUSH4State *env = &cpu->env;
+
+ env->id = SH_CPU_SH7751R;
+ env->features = SH_FEATURE_BCR3_AND_BCR4;
+}
+
+static void sh7751r_class_init(ObjectClass *oc, void *data)
+{
+ SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+ scc->name = "SH7751R";
+ scc->pvr = 0x04050005;
+ scc->prr = 0x00000113;
+ scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
+}
+
+static const TypeInfo sh7751r_type_info = {
+ .name = TYPE_SH7751R_CPU,
+ .parent = TYPE_SUPERH_CPU,
+ .class_init = sh7751r_class_init,
+ .instance_init = sh7751r_cpu_initfn,
+};
+
+static void sh7785_cpu_initfn(Object *obj)
+{
+ SuperHCPU *cpu = SUPERH_CPU(obj);
+ CPUSH4State *env = &cpu->env;
+
+ env->id = SH_CPU_SH7785;
+ env->features = SH_FEATURE_SH4A;
+}
+
+static void sh7785_class_init(ObjectClass *oc, void *data)
+{
+ SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+ scc->name = "SH7785";
+ scc->pvr = 0x10300700;
+ scc->prr = 0x00000200;
+ scc->cvr = 0x71440211;
+}
+
+static const TypeInfo sh7785_type_info = {
+ .name = TYPE_SH7785_CPU,
+ .parent = TYPE_SUPERH_CPU,
+ .class_init = sh7785_class_init,
+ .instance_init = sh7785_cpu_initfn,
+};
+
static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
{
SuperHCPU *cpu = SUPERH_CPU(dev);
scc->parent_reset = cc->reset;
cc->reset = superh_cpu_reset;
+ cc->class_by_name = superh_cpu_class_by_name;
+ cc->do_interrupt = superh_cpu_do_interrupt;
dc->vmsd = &vmstate_sh_cpu;
}
.parent = TYPE_CPU,
.instance_size = sizeof(SuperHCPU),
.instance_init = superh_cpu_initfn,
- .abstract = false,
+ .abstract = true,
.class_size = sizeof(SuperHCPUClass),
.class_init = superh_cpu_class_init,
};
static void superh_cpu_register_types(void)
{
type_register_static(&superh_cpu_type_info);
+ type_register_static(&sh7750r_type_info);
+ type_register_static(&sh7751r_type_info);
+ type_register_static(&sh7785_type_info);
}
type_init(superh_cpu_register_types)
CPU_COMMON
int id; /* CPU model */
- uint32_t pvr; /* Processor Version Register */
- uint32_t prr; /* Processor Revision Register */
- uint32_t cvr; /* Cache Version Register */
void *intc_handle;
int in_sleep; /* SR_BL ignored during sleep */
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
-void do_interrupt(CPUSH4State * env);
void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#if !defined(CONFIG_USER_ONLY)
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUSH4State *env = &SUPERH_CPU(cpu)->env;
-
- return env->interrupt_request & CPU_INTERRUPT_HARD;
+ return cpu->interrupt_request & CPU_INTERRUPT_HARD;
}
#include "exec/exec-all.h"
#if defined(CONFIG_USER_ONLY)
-void do_interrupt (CPUSH4State *env)
+void superh_cpu_do_interrupt(CPUState *cs)
{
- env->exception_index = -1;
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+
+ env->exception_index = -1;
}
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
#define MMU_DADDR_ERROR_READ (-12)
#define MMU_DADDR_ERROR_WRITE (-13)
-void do_interrupt(CPUSH4State * env)
+void superh_cpu_do_interrupt(CPUState *cs)
{
- int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+ int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
int do_exp, irq_vector = env->exception_index;
/* prioritize exceptions over interrupts */
void helper_sleep(CPUSH4State *env)
{
- env->halted = 1;
+ CPUState *cs = CPU(sh_env_get_cpu(env));
+
+ cs->halted = 1;
env->in_sleep = 1;
raise_exception(env, EXCP_HLT, 0);
}
}
}
-typedef struct {
- const char *name;
- int id;
- uint32_t pvr;
- uint32_t prr;
- uint32_t cvr;
- uint32_t features;
-} sh4_def_t;
-
-static sh4_def_t sh4_defs[] = {
- {
- .name = "SH7750R",
- .id = SH_CPU_SH7750R,
- .pvr = 0x00050000,
- .prr = 0x00000100,
- .cvr = 0x00110000,
- .features = SH_FEATURE_BCR3_AND_BCR4,
- }, {
- .name = "SH7751R",
- .id = SH_CPU_SH7751R,
- .pvr = 0x04050005,
- .prr = 0x00000113,
- .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */
- .features = SH_FEATURE_BCR3_AND_BCR4,
- }, {
- .name = "SH7785",
- .id = SH_CPU_SH7785,
- .pvr = 0x10300700,
- .prr = 0x00000200,
- .cvr = 0x71440211,
- .features = SH_FEATURE_SH4A,
- },
-};
-
-static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
-{
- int i;
-
- if (strcasecmp(name, "any") == 0)
- return &sh4_defs[0];
-
- for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
- if (strcasecmp(name, sh4_defs[i].name) == 0)
- return &sh4_defs[i];
-
- return NULL;
-}
-
-void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
- (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
-}
-
-static void cpu_register(CPUSH4State *env, const sh4_def_t *def)
-{
- env->pvr = def->pvr;
- env->prr = def->prr;
- env->cvr = def->cvr;
- env->id = def->id;
-}
-
-SuperHCPU *cpu_sh4_init(const char *cpu_model)
-{
- SuperHCPU *cpu;
- CPUSH4State *env;
- const sh4_def_t *def;
-
- def = cpu_sh4_find_by_name(cpu_model);
- if (!def)
- return NULL;
- cpu = SUPERH_CPU(object_new(TYPE_SUPERH_CPU));
- env = &cpu->env;
- env->features = def->features;
- env->cpu_model_str = cpu_model;
- cpu_register(env, def);
-
- object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
-
- return cpu;
-}
-
static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
{
TranslationBlock *tb;
#define ENV_OFFSET offsetof(SPARCCPU, env)
+void sparc_cpu_do_interrupt(CPUState *cpu);
+
#endif
scc->parent_reset = cc->reset;
cc->reset = sparc_cpu_reset;
+
+ cc->do_interrupt = sparc_cpu_do_interrupt;
}
static const TypeInfo sparc_cpu_type_info = {
void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
/* int_helper.c */
-void do_interrupt(CPUSPARCState *env);
void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
/* sun4m.c, sun4u.c */
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUSPARCState *env1 = &SPARC_CPU(cpu)->env;
+ SPARCCPU *sparc_cpu = SPARC_CPU(cpu);
+ CPUSPARCState *env1 = &sparc_cpu->env;
- return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
+ return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_interrupts_enabled(env1);
}
#ifndef TARGET_SPARC64
void helper_power_down(CPUSPARCState *env)
{
- env->halted = 1;
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
+
+ cs->halted = 1;
env->exception_index = EXCP_HLT;
env->pc = env->npc;
env->npc = env->pc + 4;
};
#endif
-void do_interrupt(CPUSPARCState *env)
+void sparc_cpu_do_interrupt(CPUState *cs)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
int cwp, intno = env->exception_index;
/* Compute PSR before exposing state. */
};
#endif
-void do_interrupt(CPUSPARCState *env)
+void sparc_cpu_do_interrupt(CPUState *cs)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
int intno = env->exception_index;
trap_state *tsptr;
#define ENV_OFFSET offsetof(UniCore32CPU, env)
+void uc32_cpu_do_interrupt(CPUState *cpu);
+
#endif
dc->realize = uc32_cpu_realizefn;
cc->class_by_name = uc32_cpu_class_by_name;
+ cc->do_interrupt = uc32_cpu_do_interrupt;
dc->vmsd = &vmstate_uc32_cpu;
}
}
void uc32_translate_init(void);
-void do_interrupt(CPUUniCore32State *);
void switch_mode(CPUUniCore32State *, int);
static inline bool cpu_has_work(CPUState *cpu)
{
- CPUUniCore32State *env = &UNICORE32_CPU(cpu)->env;
-
- return env->interrupt_request &
+ return cpu->interrupt_request &
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
}
}
}
-void do_interrupt(CPUUniCore32State *env)
+void uc32_cpu_do_interrupt(CPUState *cs)
{
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+ CPUUniCore32State *env = &cpu->env;
+
cpu_abort(env, "NO interrupt in user mode\n");
}
}
/* Handle a CPU exception. */
-void do_interrupt(CPUUniCore32State *env)
+void uc32_cpu_do_interrupt(CPUState *cs)
{
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+ CPUUniCore32State *env = &cpu->env;
uint32_t addr;
int new_mode;
/* The PC already points to the proper instruction. */
env->regs[30] = env->regs[31];
env->regs[31] = addr;
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
#define ENV_OFFSET offsetof(XtensaCPU, env)
+void xtensa_cpu_do_interrupt(CPUState *cpu);
+
#endif
xcc->parent_reset = cc->reset;
cc->reset = xtensa_cpu_reset;
+ cc->do_interrupt = xtensa_cpu_do_interrupt;
dc->vmsd = &vmstate_xtensa_cpu;
}
void xtensa_breakpoint_handler(CPUXtensaState *env);
int cpu_xtensa_exec(CPUXtensaState *s);
void xtensa_register_core(XtensaConfigList *node);
-void do_interrupt(CPUXtensaState *s);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
}
}
-void do_interrupt(CPUXtensaState *env)
+void xtensa_cpu_do_interrupt(CPUState *cs)
{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
+
if (env->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT,
"%s(EXC_IRQ) level = %d, cintlevel = %d, "
void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
{
+ CPUState *cpu;
+
env->pc = pc;
env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
(intlevel << PS_INTLEVEL_SHIFT);
return;
}
+ cpu = CPU(xtensa_env_get_cpu(env));
env->halt_clock = qemu_get_clock_ns(vm_clock);
- env->halted = 1;
+ cpu->halted = 1;
if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
xtensa_rearm_ccompare_timer(env);
}
tb_phys_invalidate(tb, -1);
if (cpu != NULL) {
cpu->current_tb = saved_tb;
- if (env && env->interrupt_request && cpu->current_tb) {
- cpu_interrupt(env, env->interrupt_request);
+ if (cpu->interrupt_request && cpu->current_tb) {
+ cpu_interrupt(cpu, cpu->interrupt_request);
}
}
}
#ifndef CONFIG_USER_ONLY
/* mask must never be zero, except for A20 change call */
-static void tcg_handle_interrupt(CPUArchState *env, int mask)
+static void tcg_handle_interrupt(CPUState *cpu, int mask)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
int old_mask;
- old_mask = env->interrupt_request;
- env->interrupt_request |= mask;
+ old_mask = cpu->interrupt_request;
+ cpu->interrupt_request |= mask;
/*
* If called from iothread context, wake the target cpu in
#else /* CONFIG_USER_ONLY */
-void cpu_interrupt(CPUArchState *env, int mask)
+void cpu_interrupt(CPUState *cpu, int mask)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
- env->interrupt_request |= mask;
+ cpu->interrupt_request |= mask;
cpu->tcg_exit_req = 1;
}
static void xen_reset_vcpu(void *opaque)
{
- CPUArchState *env = opaque;
+ CPUState *cpu = opaque;
- env->halted = 1;
+ cpu->halted = 1;
}
void xen_vcpu_init(void)
{
if (first_cpu != NULL) {
- qemu_register_reset(xen_reset_vcpu, first_cpu);
- xen_reset_vcpu(first_cpu);
+ CPUState *cpu = ENV_GET_CPU(first_cpu);
+
+ qemu_register_reset(xen_reset_vcpu, cpu);
+ xen_reset_vcpu(cpu);
}
/* if rtc_clock is left to default (host_clock), disable it */
if (rtc_clock == host_clock) {