ASoC: SOF: intel: add sdw_shim/alh_base to sof_intel_dsp_desc

sdw_shim_base and sdw_alh_base are platform-dependent. This change allow
us to define different sdw shim/alh base for each platform.

Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20210723115451.7245-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/sof/intel/cnl.c b/sound/soc/sof/intel/cnl.c
index 821f25fbcf089dc0ca82aeae9fc6cc137d495a08..acc07cfbc8e387445ce8168a469d725aa81a28be 100644 (file)
--- a/sound/soc/sof/intel/cnl.c
+++ b/sound/soc/sof/intel/cnl.c
@@ -347,6 +347,8 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        .rom_init_timeout       = 300,
        .ssp_count = CNL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+       .sdw_shim_base = SDW_SHIM_BASE,
+       .sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -363,5 +365,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+       .sdw_shim_base = SDW_SHIM_BASE,
+       .sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

diff --git a/sound/soc/sof/intel/icl.c b/sound/soc/sof/intel/icl.c
index 88a74be8a0c141f2b7565fe1fad580cfe920bd3f..74a14b24794ce827359765d178989b5252235866 100644 (file)
--- a/sound/soc/sof/intel/icl.c
+++ b/sound/soc/sof/intel/icl.c
@@ -142,5 +142,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+       .sdw_shim_base = SDW_SHIM_BASE,
+       .sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);

diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
index 529f68d0ca47c5153d0d3d74e39748cb1e502d1c..ee031248d834e1db06fc5b9fcef09af1502a8922 100644 (file)
--- a/sound/soc/sof/intel/shim.h
+++ b/sound/soc/sof/intel/shim.h
@@ -164,6 +164,8 @@ struct sof_intel_dsp_desc {
        int rom_init_timeout;
        int ssp_count;                  /* ssp count of the platform */
        int ssp_base_offset;            /* base address of the SSPs */
+       u32 sdw_shim_base;
+       u32 sdw_alh_base;
 };
 
 extern const struct snd_sof_dsp_ops sof_tng_ops;

diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c
index 2ed7883044147c4187d72048b0e27803cb9a7dbb..73aa45bc6f2b0c59b1561c9fcf55fe1fee66353b 100644 (file)
--- a/sound/soc/sof/intel/tgl.c
+++ b/sound/soc/sof/intel/tgl.c
@@ -137,6 +137,8 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+       .sdw_shim_base = SDW_SHIM_BASE,
+       .sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -153,6 +155,8 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+       .sdw_shim_base = SDW_SHIM_BASE,
+       .sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -169,6 +173,8 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+       .sdw_shim_base = SDW_SHIM_BASE,
+       .sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 
@@ -185,5 +191,7 @@ const struct sof_intel_dsp_desc adls_chip_info = {
        .rom_init_timeout       = 300,
        .ssp_count = ICL_SSP_COUNT,
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
+       .sdw_shim_base = SDW_SHIM_BASE,
+       .sdw_alh_base = SDW_ALH_BASE,
 };
 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);