Merge tag 'pull-target-arm-20230410' of https://git.linaro.org/people/pmaydell/qemu...

target-arm: Fix bug where we weren't initializing
            guarded bit state when combining S1/S2 attrs

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# gpg: Signature made Mon 10 Apr 2023 15:12:11 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230410' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Copy guarded bit in combine_cacheattrs
  target/arm: PTE bit GP only applies to stage1

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>