Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux

Pull clk framework update from Michael Turquette:
 "The common clk framework changes for 3.7 are dominated by ARM platform
  ports to the framework along with one MIPS port, one MFD port, one
  minor framework enhancement and one helper function for platforms
  expressing their clock data through device tree."

* tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux:
  clk: add of_clk_src_onecell_get() support
  clk: ux500: Define smp_twd clock for u8500
  mfd: dbx500: Provide a more accurate smp_twd clock
  clk: ux500: Support for prmcu_rate clock
  clk: Provide option for clk_get_rate to issue hw for new rate
  clock: max77686: Add driver for Maxim 77686 32Khz crystal oscillator.
  ARM: ux500: Switch to use common clock framework
  clk: ux500: Clock definitions for u8500
  clk: ux500: First version of clock definitions for ux500
  clk: ux500: Adapt PRCMU and PRCC clocks for common clk
  clk: versatile: make config option boolean
  clk: add Loongson1B clock support
  arm: mmp: make all SOCs use common clock by default
  clk: mmp: add clock definition for mmp2
  clk: mmp: add clock definition for pxa910
  clk: mmp: add clock definition for pxa168
  clk: mmp: add mmp specific clocks
  clk: convert ARM RealView to common clk
  clk: prima2: move from arch/arm/mach to drivers/clk
  ARM: PRIMA2: convert to common clk and finish full clk tree

diff --combined arch/arm/Kconfig
index 2f88d8d9770116014f7ff55e80d98c65fbb191ed,1a01ffa331d04d1fe9c2fa41295aa5eb9fe4b0db..de325f4615bd0ae6a76b9ba82b828a928cfdcbd6
--- 1/arch/arm/Kconfig
--- 2/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@@ -6,7 -6,7 +6,7 @@@ config AR
        select HAVE_DMA_API_DEBUG
        select HAVE_IDE if PCI || ISA || PCMCIA
        select HAVE_DMA_ATTRS
 -      select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
 +      select HAVE_DMA_CONTIGUOUS if MMU
        select HAVE_MEMBLOCK
        select RTC_LIB
        select SYS_SUPPORTS_APM_EMULATION
@@@ -273,7 -273,7 +273,7 @@@ config ARCH_INTEGRATO
        select ARM_AMBA
        select ARCH_HAS_CPUFREQ
        select COMMON_CLK
-       select CLK_VERSATILE
+       select COMMON_CLK_VERSATILE
        select HAVE_TCM
        select ICST
        select GENERIC_CLOCKEVENTS
@@@ -289,13 -289,12 +289,12 @@@
  config ARCH_REALVIEW
        bool "ARM Ltd. RealView family"
        select ARM_AMBA
-       select CLKDEV_LOOKUP
-       select HAVE_MACH_CLKDEV
+       select COMMON_CLK
+       select COMMON_CLK_VERSATILE
        select ICST
        select GENERIC_CLOCKEVENTS
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select PLAT_VERSATILE
-       select PLAT_VERSATILE_CLOCK
        select PLAT_VERSATILE_CLCD
        select ARM_TIMER_SP804
        select GPIO_PL061 if GPIOLIB
@@@ -413,7 -412,7 +412,7 @@@ config ARCH_PRIMA
        select NO_IOPORT
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
-       select CLKDEV_LOOKUP
+       select COMMON_CLK
        select GENERIC_IRQ_CHIP
        select MIGHT_HAVE_CACHE_L2X0
        select PINCTRL
@@@ -2144,7 -2143,6 +2143,7 @@@ source "drivers/cpufreq/Kconfig
  config CPU_FREQ_IMX
        tristate "CPUfreq driver for i.MX CPUs"
        depends on ARCH_MXC && CPU_FREQ
 +      select CPU_FREQ_TABLE
        help
          This enables the CPUfreq driver for i.MX CPUs.
  

diff --combined arch/arm/mach-ux500/Kconfig
index 53d3d46dec1290b4265a3c3c26d7ffc0449f223e,2d76e4f9c97e91e1f597c31af364188f12decd7d..a258996d954b9fc5f260196f48f8e8449a28d277
--- 1/arch/arm/mach-ux500/Kconfig
--- 2/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@@ -11,6 -11,7 +11,7 @@@ config UX500_SOC_COMMO
        select CACHE_L2X0
        select PINCTRL
        select PINCTRL_NOMADIK
+       select COMMON_CLK
  
  config UX500_SOC_DB8500
        bool
@@@ -41,6 -42,7 +42,6 @@@ config MACH_HREFV6
  config MACH_SNOWBALL
        bool "U8500 Snowball platform"
        select MACH_MOP500
 -      select LEDS_GPIO
        help
          Include support for the snowball development platform.
  

diff --combined drivers/clk/Makefile
index 72ce247a0e8d5c08395fe92c9163a8c376c555bc,6327536b4900ae5e06d8da313af721c9dc4b9c4a..b7b862077d88515cee0e4405dc062947cd15a99f
--- 1/drivers/clk/Makefile
--- 2/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@@ -1,5 -1,4 +1,5 @@@
  # common clock types
 +obj-$(CONFIG_HAVE_CLK)                += clk-devres.o
  obj-$(CONFIG_CLKDEV_LOOKUP)   += clkdev.o
  obj-$(CONFIG_COMMON_CLK)      += clk.o clk-fixed-rate.o clk-gate.o \
                                   clk-mux.o clk-divider.o clk-fixed-factor.o
@@@ -10,7 -9,14 +10,14 @@@ obj-$(CONFIG_ARCH_MXS)               += mxs
  obj-$(CONFIG_ARCH_SOCFPGA)    += socfpga/
  obj-$(CONFIG_PLAT_SPEAR)      += spear/
  obj-$(CONFIG_ARCH_U300)               += clk-u300.o
- obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/
+ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
+ obj-$(CONFIG_ARCH_PRIMA2)     += clk-prima2.o
+ ifeq ($(CONFIG_COMMON_CLK), y)
+ obj-$(CONFIG_ARCH_MMP)                += mmp/
+ endif
+ obj-$(CONFIG_MACH_LOONGSON1)  += clk-ls1x.o
+ obj-$(CONFIG_ARCH_U8500)      += ux500/
  
  # Chip specific
  obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
+ obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o

diff --combined drivers/mfd/db8500-prcmu.c
index 0e63cdd9b52abc44666c57994623e120f11644b2,6b37e2d6ed8f5dd579c9ba655373641463ccfe99..6b67edbdbd013e5531527aa3a7316362009e4f4e
--- 1/drivers/mfd/db8500-prcmu.c
--- 2/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@@ -418,6 -418,9 +418,9 @@@ static struct 
  
  static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
  
+ /* Functions definition */
+ static void compute_armss_rate(void);
+ 
  /* Spinlocks */
  static DEFINE_SPINLOCK(prcmu_lock);
  static DEFINE_SPINLOCK(clkout_lock);
@@@ -517,6 -520,7 +520,7 @@@ static struct dsiescclk dsiescclk[3] = 
        }
  };
  
+ 
  /*
  * Used by MCDE to setup all necessary PRCMU registers
  */
@@@ -1013,6 -1017,7 +1017,7 @@@ int db8500_prcmu_set_arm_opp(u8 opp
                (mb1_transfer.ack.arm_opp != opp))
                r = -EIO;
  
+       compute_armss_rate();
        mutex_unlock(&mb1_transfer.lock);
  
        return r;
@@@ -1612,6 -1617,7 +1617,7 @@@ static unsigned long pll_rate(void __io
        if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
                (val & PRCM_PLL_FREQ_DIV2EN) &&
                ((reg == PRCM_PLLSOC0_FREQ) ||
+                (reg == PRCM_PLLARM_FREQ) ||
                 (reg == PRCM_PLLDDR_FREQ))))
                div *= 2;
  
@@@ -1661,6 -1667,39 +1667,39 @@@ static unsigned long clock_rate(u8 cloc
        else
                return 0;
  }
+ static unsigned long latest_armss_rate;
+ static unsigned long armss_rate(void)
+ {
+       return latest_armss_rate;
+ }
+ 
+ static void compute_armss_rate(void)
+ {
+       u32 r;
+       unsigned long rate;
+ 
+       r = readl(PRCM_ARM_CHGCLKREQ);
+ 
+       if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
+               /* External ARMCLKFIX clock */
+ 
+               rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
+ 
+               /* Check PRCM_ARM_CHGCLKREQ divider */
+               if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
+                       rate /= 2;
+ 
+               /* Check PRCM_ARMCLKFIX_MGT divider */
+               r = readl(PRCM_ARMCLKFIX_MGT);
+               r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
+               rate /= r;
+ 
+       } else {/* ARM PLL */
+               rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
+       }
+ 
+       latest_armss_rate = rate;
+ }
  
  static unsigned long dsiclk_rate(u8 n)
  {
@@@ -1707,6 -1746,8 +1746,8 @@@ unsigned long prcmu_clock_rate(u8 clock
                return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
        else if (clock == PRCMU_PLLSOC1)
                return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
+       else if (clock == PRCMU_ARMSS)
+               return armss_rate();
        else if (clock == PRCMU_PLLDDR)
                return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
        else if (clock == PRCMU_PLLDSI)
@@@ -2693,6 -2734,7 +2734,7 @@@ void __init db8500_prcmu_early_init(voi
                                         handle_simple_irq);
                set_irq_flags(irq, IRQF_VALID);
        }
+       compute_armss_rate();
  }
  
  static void __init init_prcm_registers(void)
@@@ -3010,7 -3052,7 +3052,7 @@@ static int __devinit db8500_prcmu_probe
                prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
  
        err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
 -                      ARRAY_SIZE(db8500_prcmu_devs), NULL, 0);
 +                            ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL);
        if (err) {
                pr_err("prcmu: Failed to add subdevices\n");
                return err;