soundwire: registers: add definitions for clearable interrupt fields

DP0 has reserved fields and the read-only SDCA_CASCADE bit. We should
not try to write values in these fields, so add a formal definition
for clearable interrupts to be used in DP0 interrupt handling.

DPN also has reserved fields so add definitions for clearable
interrupts as well.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20201124013318.8963-4-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/include/linux/soundwire/sdw_registers.h b/include/linux/soundwire/sdw_registers.h
index f420e80597798353c0673f2205c1f214a12fd2f5..0cb1a22685b84c8ae820bba65541342f1ae394ca 100644 (file)
--- a/include/linux/soundwire/sdw_registers.h
+++ b/include/linux/soundwire/sdw_registers.h
@@ -41,6 +41,12 @@
 #define SDW_DP0_INT_IMPDEF1                    BIT(5)
 #define SDW_DP0_INT_IMPDEF2                    BIT(6)
 #define SDW_DP0_INT_IMPDEF3                    BIT(7)
+#define SDW_DP0_INTERRUPTS                     (SDW_DP0_INT_TEST_FAIL | \
+                                                SDW_DP0_INT_PORT_READY | \
+                                                SDW_DP0_INT_BRA_FAILURE | \
+                                                SDW_DP0_INT_IMPDEF1 | \
+                                                SDW_DP0_INT_IMPDEF2 | \
+                                                SDW_DP0_INT_IMPDEF3)
 
 #define SDW_DP0_PORTCTRL_DATAMODE              GENMASK(3, 2)
 #define SDW_DP0_PORTCTRL_NXTINVBANK            BIT(4)
@@ -241,6 +247,11 @@
 #define SDW_DPN_INT_IMPDEF1                    BIT(5)
 #define SDW_DPN_INT_IMPDEF2                    BIT(6)
 #define SDW_DPN_INT_IMPDEF3                    BIT(7)
+#define SDW_DPN_INTERRUPTS                     (SDW_DPN_INT_TEST_FAIL | \
+                                                SDW_DPN_INT_PORT_READY | \
+                                                SDW_DPN_INT_IMPDEF1 | \
+                                                SDW_DPN_INT_IMPDEF2 | \
+                                                SDW_DPN_INT_IMPDEF3)
 
 #define SDW_DPN_PORTCTRL_FLOWMODE              GENMASK(1, 0)
 #define SDW_DPN_PORTCTRL_DATAMODE              GENMASK(3, 2)