target-mips: fix xtlb exception for loongson

Loongson 2E and 2F use the same entry for xtlb and tlb exception, at
offset 0x000.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

diff --git a/target-mips/helper.c b/target-mips/helper.c
index ea221ab53f1e52c7bf7c7fb57f393b538fe524d4..de2ed7d2c76ea6ea1e67cc405b48516c5398d9c9 100644 (file)
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -491,7 +491,8 @@ void do_interrupt (CPUState *env)
             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 
-            if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
+            if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
+                (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
                 offset = 0x080;
             else
 #endif
@@ -507,7 +508,8 @@ void do_interrupt (CPUState *env)
             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 
-            if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
+            if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
+                (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
                 offset = 0x080;
             else
 #endif