arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0

Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
to PCIe and QSGMII (multi-link SERDES).

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210105151421.23237-6-kishon@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 331b388e1d1b2c429e3acf38da96a322192b1ff4..def98f563336b12705020a76b7598361adb454e4 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -8,6 +8,7 @@
 #include "k3-j7200-som-p0.dtsi"
 #include <dt-bindings/net/ti-dp83867.h>
 #include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
        chosen {
@@ -218,3 +219,25 @@
                ti,adc-channels = <0 1 2 3 4 5 6 7>;
        };
 };
+
+&serdes_refclk {
+       clock-frequency = <100000000>;
+};
+
+&serdes0 {
+       serdes0_pcie_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+       };
+
+       serdes0_qsgmii_link: phy@1 {
+               reg = <2>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_QSGMII>;
+               resets = <&serdes_wiz0 3>;
+       };
+};