drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid

Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 752032eba6ecaa05cba99f7e2b4f7100826dab4e..6c52363d566233b8338f72187311d6a9d33f3ce3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -55,6 +55,7 @@
  * 2. Async ring
  */
 #define GFX10_NUM_GFX_RINGS_NV1X       1
+#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid     2
 #define GFX10_MEC_HPD_SIZE     2048
 
 #define F32_CE_PROGRAM_RAM_SIZE                65536
@@ -7057,7 +7058,18 @@ static int gfx_v10_0_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-       adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
+       switch (adev->asic_type) {
+       case CHIP_NAVI10:
+       case CHIP_NAVI14:
+       case CHIP_NAVI12:
+               adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
+               break;
+       case CHIP_SIENNA_CICHLID:
+               adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
+               break;
+       default:
+               break;
+       }
 
        adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;