};
-static void write_page (CPUState *env, uint32_t nport, uint32_t data)
+static void write_page (void *opaque, uint32_t nport, uint32_t data)
{
int ichan;
int ncont;
return ff;
}
-static uint32_t read_chan (CPUState *env, uint32_t nport)
+static uint32_t read_chan (void *opaque, uint32_t nport)
{
int ff;
int ncont, ichan, nreg;
return (val >> (ncont + (ff << 3))) & 0xff;
}
-static void write_chan (CPUState *env, uint32_t nport, uint32_t data)
+static void write_chan (void *opaque, uint32_t nport, uint32_t data)
{
int ncont, ichan, nreg;
struct dma_regs *r;
}
}
-static void write_cont (CPUState *env, uint32_t nport, uint32_t data)
+static void write_cont (void *opaque, uint32_t nport, uint32_t data)
{
int iport, ichan, ncont;
struct dma_cont *d;
int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
for (i = 0; i < 8; i++) {
- register_ioport_write (i, 1, write_chan, 1);
+ register_ioport_write (i, 1, 1, write_chan, NULL);
- register_ioport_write (0xc0 + (i << 1), 1, write_chan, 1);
+ register_ioport_write (0xc0 + (i << 1), 1, 1, write_chan, NULL);
- register_ioport_read (i, 1, read_chan, 1);
- register_ioport_read (0xc0 + (i << 1), 1, read_chan, 1);
+ register_ioport_read (i, 1, 1, read_chan, NULL);
+ register_ioport_read (0xc0 + (i << 1), 1, 1, read_chan, NULL);
}
for (i = 0; i < LENOFA (page_port_list); i++) {
- register_ioport_write (page_port_list[i] + 0x80, 1, write_page, 1);
- register_ioport_write (page_port_list[i] + 0x88, 1, write_page, 1);
+ register_ioport_write (page_port_list[i] + 0x80, 1, 1, write_page, NULL);
+ register_ioport_write (page_port_list[i] + 0x88, 1, 1, write_page, NULL);
}
for (i = 0; i < 8; i++) {
- register_ioport_write (i + 8, 1, write_cont, 1);
- register_ioport_write (0xd0 + (i << 1), 1, write_cont, 1);
+ register_ioport_write (i + 8, 1, 1, write_cont, NULL);
+ register_ioport_write (0xd0 + (i << 1), 1, 1, write_cont, NULL);
}
write_cont (NULL, 0x0d, 0);
#endif
#define IO_READ_PROTO(name) \
- uint32_t name (struct CPUState *env, uint32_t nport)
+ uint32_t name (void *opaque, uint32_t nport)
#define IO_WRITE_PROTO(name) \
- void name (struct CPUState *env, uint32_t nport, uint32_t val)
+ void name (void *opaque, uint32_t nport, uint32_t val)
static struct {
int ver_lo;
static IO_WRITE_PROTO(mixer_write_indexw)
{
- mixer_write_indexb (env, nport, val & 0xff);
- mixer_write_datab (env, nport, (val >> 8) & 0xff);
+ mixer_write_indexb (opaque, nport, val & 0xff);
+ mixer_write_datab (opaque, nport, (val >> 8) & 0xff);
}
static IO_READ_PROTO(mixer_read)
}
for (i = 0; i < LENOFA (dsp_write_ports); i++) {
- register_ioport_write (sb.port + dsp_write_ports[i], 1, dsp_write, 1);
+ register_ioport_write (sb.port + dsp_write_ports[i], 1, 1, dsp_write, NULL);
}
for (i = 0; i < LENOFA (dsp_read_ports); i++) {
- register_ioport_read (sb.port + dsp_read_ports[i], 1, dsp_read, 1);
+ register_ioport_read (sb.port + dsp_read_ports[i], 1, 1, dsp_read, NULL);
}
- register_ioport_write (sb.port + 0x4, 1, mixer_write_indexb, 1);
- register_ioport_write (sb.port + 0x4, 1, mixer_write_indexw, 2);
- register_ioport_read (sb.port + 0x5, 1, mixer_read, 1);
- register_ioport_write (sb.port + 0x5, 1, mixer_write_datab, 1);
+ register_ioport_write (sb.port + 0x4, 1, 1, mixer_write_indexb, NULL);
+ register_ioport_write (sb.port + 0x4, 1, 2, mixer_write_indexw, NULL);
+ register_ioport_read (sb.port + 0x5, 1, 1, mixer_read, NULL);
+ register_ioport_write (sb.port + 0x5, 1, 1, mixer_write_datab, NULL);
DMA_register_channel (sb.hdma, SB_read_DMA, NULL);
DMA_register_channel (sb.dma, SB_read_DMA, NULL);