mmc: sdhci-xenon: fix PHY init clock stability

Each time SD/mmc phy is initialized, at times, in some of
the attempts, phy fails to completes its initialization
which results into timeout error. Per the HW spec, it is
a pre-requisite to ensure a stable SD clock before a phy
initialization is attempted.

Fixes: 06c8b667ff5b ("mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC")
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Elad Nachman <enachman@marvell.com>
Link: https://lore.kernel.org/r/20240222200930.1277665-1-enachman@marvell.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
index 8cf3a375de659a6d98b7dcfc2f4e2be09f7c4a5d..c3096230a969e1588b00e1a6ded970f0b54e2645 100644 (file)
--- a/drivers/mmc/host/sdhci-xenon-phy.c
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -11,6 +11,7 @@
 #include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/ktime.h>
+#include <linux/iopoll.h>
 #include <linux/of_address.h>
 
 #include "sdhci-pltfm.h"
@@ -216,6 +217,19 @@ static int xenon_alloc_emmc_phy(struct sdhci_host *host)
        return 0;
 }
 
+static int xenon_check_stability_internal_clk(struct sdhci_host *host)
+{
+       u32 reg;
+       int err;
+
+       err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE,
+                               1100, 20000, false, host, SDHCI_CLOCK_CONTROL);
+       if (err)
+               dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n");
+
+       return err;
+}
+
 /*
  * eMMC 5.0/5.1 PHY init/re-init.
  * eMMC PHY init should be executed after:
@@ -232,6 +246,11 @@ static int xenon_emmc_phy_init(struct sdhci_host *host)
        struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
        struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
 
+       int ret = xenon_check_stability_internal_clk(host);
+
+       if (ret)
+               return ret;
+
        reg = sdhci_readl(host, phy_regs->timing_adj);
        reg |= XENON_PHY_INITIALIZAION;
        sdhci_writel(host, reg, phy_regs->timing_adj);