arm64: dts: imx8mn-evk: Align pin configuration group names with schema

Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 76e0225729b1c71bb2e40f037e3aae88c040bd1a..7f4b904e9982d66e7f9c2283e43d2b7cdaadc2e6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -223,13 +223,13 @@
                >;
        };
 
-       pinctrl_pmic: pmicirq {
+       pinctrl_pmic: pmicirqgrp {
                fsl,pins = <
                        MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
                >;
        };
 
-       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
                fsl,pins = <
                        MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
                >;
@@ -248,7 +248,7 @@
                >;
        };
 
-       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                fsl,pins = <
                        MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
                >;
@@ -266,7 +266,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
                        MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
@@ -278,7 +278,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
                        MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
@@ -306,7 +306,7 @@
                >;
        };
 
-       pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+       pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
                fsl,pins = <
                        MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
                        MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
@@ -322,7 +322,7 @@
                >;
        };
 
-       pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+       pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
                fsl,pins = <
                        MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
                        MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6