for_each_if((encoder_mask) & \
drm_encoder_mask(&intel_encoder->base))
-#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \
+#define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
intel_encoder_can_psr(intel_encoder))
for_each_intel_encoder(dev, intel_encoder) \
for_each_if(intel_encoder_is_dp(intel_encoder))
-#define for_each_intel_encoder_can_psr(dev, intel_encoder) \
+#define for_each_intel_encoder_with_psr(dev, intel_encoder) \
for_each_intel_encoder((dev), (intel_encoder)) \
for_each_if(intel_encoder_can_psr(intel_encoder))
return -ENODEV;
/* Find the first EDP which supports PSR */
- for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
intel_dp = enc_to_intel_dp(encoder);
break;
}
if (!HAS_PSR(dev_priv))
return ret;
- for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
if (!HAS_PSR(dev_priv))
return -ENODEV;
- for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
// TODO: split to each transcoder's PSR debug state
!crtc_state->enable_psr2_sel_fetch)
return;
- for_each_intel_encoder_mask_can_psr(&dev_priv->drm, encoder,
- crtc_state->uapi.encoder_mask) {
+ for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
+ crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (!intel_dp->psr.enabled)
if (!new_crtc_state->has_psr)
return;
- for_each_intel_encoder_mask_can_psr(&dev_priv->drm, encoder,
- new_crtc_state->uapi.encoder_mask) {
+ for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
+ new_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
u32 psr_status;
if (origin == ORIGIN_FLIP)
return;
- for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
{
struct intel_encoder *encoder;
- for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (de_iir & DE_EDP_PSR_INT_HSW) {
struct intel_encoder *encoder;
- for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
u32 psr_iir = intel_uncore_read(&dev_priv->uncore,
u32 psr_iir;
i915_reg_t iir_reg;
- for_each_intel_encoder_can_psr(&dev_priv->drm, encoder) {
+ for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (INTEL_GEN(dev_priv) >= 12)