/* The whole PowerPC CPU context */
#define NB_MMU_MODES 3
+#define PPC_CPU_OPCODES_LEN 0x40
+
struct CPUPPCState {
/* First are the most commonly used resources
* during translated code execution
/* Those resources are used only during code translation */
/* opcode handlers */
- opc_handler_t *opcodes[0x40];
+ opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
/* Those resources are used only in QEMU core */
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
{
opc_handler_t **tmp;
- tmp = malloc(0x20 * sizeof(opc_handler_t));
+ tmp = g_malloc(0x20 * sizeof(opc_handler_t));
fill_new_table(tmp, 0x20);
table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
#endif
}
+static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(dev);
+ CPUPPCState *env = &cpu->env;
+ int i;
+
+ for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
+ if (env->opcodes[i] != &invalid_handler) {
+ g_free(env->opcodes[i]);
+ }
+ }
+}
+
static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
{
ObjectClass *oc = (ObjectClass *)a;
pcc->parent_realize = dc->realize;
dc->realize = ppc_cpu_realizefn;
+ dc->unrealize = ppc_cpu_unrealizefn;
pcc->parent_reset = cc->reset;
cc->reset = ppc_cpu_reset;