#define IOMMU_CTRL_TSB_SHIFT 16
#define IOMMU_BASE 0x8
+#define IOMMU_FLUSH 0x10
#define IOMMU_TTE_DATA_V (1ULL << 63)
#define IOMMU_TTE_DATA_SIZE (1ULL << 61)
is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
break;
+ case IOMMU_FLUSH:
+ case IOMMU_FLUSH + 0x4:
+ break;
default:
qemu_log_mask(LOG_UNIMP,
"apb iommu: Unimplemented register write "
case IOMMU_BASE + 0x4:
val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
break;
+ case IOMMU_FLUSH:
+ case IOMMU_FLUSH + 0x4:
+ val = 0;
+ break;
default:
qemu_log_mask(LOG_UNIMP,
"apb iommu: Unimplemented register read "
/* XXX: not implemented yet */
break;
case 0x200 ... 0x217: /* IOMMU */
- iommu_config_write(is, (addr & 0xf), val, size);
+ iommu_config_write(is, (addr & 0x1f), val, size);
break;
case 0xc00 ... 0xc3f: /* PCI interrupt control */
if (addr & 4) {
/* XXX: not implemented yet */
break;
case 0x200 ... 0x217: /* IOMMU */
- val = iommu_config_read(is, (addr & 0xf), size);
+ val = iommu_config_read(is, (addr & 0x1f), size);
break;
case 0xc00 ... 0xc3f: /* PCI interrupt control */
if (addr & 4) {