UBUNTU: SAUCE: Add X86_FEATURE_ARCH_CAPABILITIES
authorStefan Bader <stefan.bader@canonical.com>
Mon, 7 May 2018 19:35:06 +0000 (21:35 +0200)
committerStefan Bader <stefan.bader@canonical.com>
Mon, 14 May 2018 10:05:34 +0000 (12:05 +0200)
Upstream added the whole CPUID 0x00000007.EDX bits under a new
individual element. Right now we have all those under the scattered
bits, so add atch capabilities there as well.

CVE-2018-3639 (x86)

Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
arch/x86/include/asm/cpufeatures.h
arch/x86/kernel/cpu/scattered.c

index 85ac88bb447c96b02b9d2f54c852a5b88dcc4ef3..b69ca29cb9c3b74edb695d234b73e022220d5ba3 100644 (file)
 #define X86_FEATURE_MBA                        ( 7*32+18) /* Memory Bandwidth Allocation */
 #define X86_FEATURE_RSB_CTXSW          ( 7*32+19) /* Fill RSB on context switches */
 #define X86_FEATURE_SPEC_CTRL          ( 7*32+20) /* Control Speculation Control */
+#define X86_FEATURE_ARCH_CAPABILITIES  ( 7*32+21) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW         ( 8*32+ 0) /* Intel TPR Shadow */
index 9651ea395812907f443339ee842ceff90322f2c5..0aeb9601a8c7e154a8e411c98795a76812272c03 100644 (file)
@@ -25,6 +25,7 @@ static const struct cpuid_bit cpuid_bits[] = {
        { X86_FEATURE_AVX512_4VNNIW,    CPUID_EDX,  2, 0x00000007, 0 },
        { X86_FEATURE_AVX512_4FMAPS,    CPUID_EDX,  3, 0x00000007, 0 },
        { X86_FEATURE_SPEC_CTRL,        CPUID_EDX, 26, 0x00000007, 0 },
+       { X86_FEATURE_ARCH_CAPABILITIES,CPUID_EDX, 29, 0x00000007, 0 },
        { X86_FEATURE_CAT_L3,           CPUID_EBX,  1, 0x00000010, 0 },
        { X86_FEATURE_CAT_L2,           CPUID_EBX,  2, 0x00000010, 0 },
        { X86_FEATURE_CDP_L3,           CPUID_ECX,  2, 0x00000010, 1 },