We now have a complete MVE emulation, so we can enable it in our
Cortex-M55 model by setting the ID registers to match those of a
Cortex-M55 with full MVE support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
cpu->revidr = 0;
cpu->pmsav7_dregion = 16;
cpu->sau_sregion = 8;
- /*
- * These are the MVFR* values for the FPU, no MVE configuration;
- * we will update them later when we implement MVE
- */
+ /* These are the MVFR* values for the FPU + full MVE configuration */
cpu->isar.mvfr0 = 0x10110221;
- cpu->isar.mvfr1 = 0x12100011;
+ cpu->isar.mvfr1 = 0x12100211;
cpu->isar.mvfr2 = 0x00000040;
cpu->isar.id_pfr0 = 0x20000030;
cpu->isar.id_pfr1 = 0x00000230;