powerpc/perf: Add platform specific check_attr_config

Add platform specific attr.config value checks. Patch
includes checks for both power9 and power10.

Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210408074504.248211-2-maddy@linux.ibm.com

diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 48b2d9a5096ca20795bc2947a309ddcd7c079246..bf9094d8205fbdff1d3ce2c04d972be08d56b8b1 100644 (file)
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -694,3 +694,45 @@ int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
 
        return num_alt;
 }
+
+int isa3XX_check_attr_config(struct perf_event *ev)
+{
+       u64 val, sample_mode;
+       u64 event = ev->attr.config;
+
+       val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
+       sample_mode = val & 0x3;
+
+       /*
+        * MMCRA[61:62] is Random Sampling Mode (SM).
+        * value of 0b11 is reserved.
+        */
+       if (sample_mode == 0x3)
+               return -EINVAL;
+
+       /*
+        * Check for all reserved value
+        * Source: Performance Monitoring Unit User Guide
+        */
+       switch (val) {
+       case 0x5:
+       case 0x9:
+       case 0xD:
+       case 0x19:
+       case 0x1D:
+       case 0x1A:
+       case 0x1E:
+               return -EINVAL;
+       }
+
+       /*
+        * MMCRA[48:51]/[52:55]) Threshold Start/Stop
+        * Events Selection.
+        * 0b11110000/0b00001111 is reserved.
+        */
+       val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
+       if (((val & 0xF0) == 0xF0) || ((val & 0xF) == 0xF))
+               return -EINVAL;
+
+       return 0;
+}

diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
index 1af0e8c97ac7bf7b473ed51a3b14e314b00649ff..b4d2a2b2b346b3144d189213b4cf719005aa7663 100644 (file)
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -280,4 +280,6 @@ void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
                                                        struct pt_regs *regs);
 void isa207_get_mem_weight(u64 *weight);
 
+int isa3XX_check_attr_config(struct perf_event *ev);
+
 #endif

diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c
index a901c1348cad0ddf571a4b2f27357bf6fa99d1c0..f9d64c63bb4a72b19018d0bbdeca8e8a516becd1 100644 (file)
--- a/arch/powerpc/perf/power10-pmu.c
+++ b/arch/powerpc/perf/power10-pmu.c
@@ -106,6 +106,18 @@ static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[])
        return num_alt;
 }
 
+static int power10_check_attr_config(struct perf_event *ev)
+{
+       u64 val;
+       u64 event = ev->attr.config;
+
+       val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
+       if (val == 0x10 || isa3XX_check_attr_config(ev))
+               return -EINVAL;
+
+       return 0;
+}
+
 GENERIC_EVENT_ATTR(cpu-cycles,                 PM_RUN_CYC);
 GENERIC_EVENT_ATTR(instructions,               PM_RUN_INST_CMPL);
 GENERIC_EVENT_ATTR(branch-instructions,                PM_BR_CMPL);
@@ -559,6 +571,7 @@ static struct power_pmu power10_pmu = {
        .attr_groups            = power10_pmu_attr_groups,
        .bhrb_nr                = 32,
        .capabilities           = PERF_PMU_CAP_EXTENDED_REGS,
+       .check_attr_config      = power10_check_attr_config,
 };
 
 int init_power10_pmu(void)

diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index 2a57e93a79dcf703b920f1b556d46d60308507e4..ff3382140d7e65a159f8be6032587d4ba2ef2422 100644 (file)
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -151,6 +151,18 @@ static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
        return num_alt;
 }
 
+static int power9_check_attr_config(struct perf_event *ev)
+{
+       u64 val;
+       u64 event = ev->attr.config;
+
+       val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
+       if (val == 0xC || isa3XX_check_attr_config(ev))
+               return -EINVAL;
+
+       return 0;
+}
+
 GENERIC_EVENT_ATTR(cpu-cycles,                 PM_CYC);
 GENERIC_EVENT_ATTR(stalled-cycles-frontend,    PM_ICT_NOSLOT_CYC);
 GENERIC_EVENT_ATTR(stalled-cycles-backend,     PM_CMPLU_STALL);
@@ -437,6 +449,7 @@ static struct power_pmu power9_pmu = {
        .attr_groups            = power9_pmu_attr_groups,
        .bhrb_nr                = 32,
        .capabilities           = PERF_PMU_CAP_EXTENDED_REGS,
+       .check_attr_config      = power9_check_attr_config,
 };
 
 int init_power9_pmu(void)