asm-generic/tlb, arch: Provide generic VIPT cache flush

The one obvious thing SH and ARM want is a sensible default for
tlb_start_vma(). (also: https://lkml.org/lkml/2004/1/15/6 )

Avoid all VIPT architectures providing their own tlb_start_vma()
implementation and rely on architectures to provide a no-op
flush_cache_range() when it is not relevant.

This patch makes tlb_start_vma() default to flush_cache_range(), which
should be right and sufficient. The only exceptions that I found where
(oddly):

  - m68k-mmu
  - sparc64
  - unicore

Those architectures appear to have flush_cache_range(), but their
current tlb_start_vma() does not call it.

No change in behavior intended.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: David Miller <davem@davemloft.net>
Cc: Guan Xuetao <gxt@pku.edu.cn>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Nick Piggin <npiggin@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rik van Riel <riel@surriel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/arc/include/asm/tlb.h b/arch/arc/include/asm/tlb.h
index a9db5f62aaf37988fe8806ac4ee0a14edf713309..7af2b373ebe753e5c7f4bb4290d250dd45209924 100644 (file)
--- a/arch/arc/include/asm/tlb.h
+++ b/arch/arc/include/asm/tlb.h
@@ -23,15 +23,6 @@ do {                                         \
  *
  * Note, read http://lkml.org/lkml/2004/1/15/6
  */
-#ifndef CONFIG_ARC_CACHE_VIPT_ALIASING
-#define tlb_start_vma(tlb, vma)
-#else
-#define tlb_start_vma(tlb, vma)                                                \
-do {                                                                   \
-       if (!tlb->fullmm)                                               \
-               flush_cache_range(vma, vma->vm_start, vma->vm_end);     \
-} while(0)
-#endif
 
 #define tlb_end_vma(tlb, vma)                                          \
 do {                                                                   \

diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
index b6823b9e94dad0c2f3b13ad867e1153d4f95c789..32b8a8187733d147eff57214ef184bfbabda9dd8 100644 (file)
--- a/arch/mips/include/asm/tlb.h
+++ b/arch/mips/include/asm/tlb.h
@@ -5,15 +5,6 @@
 #include <asm/cpu-features.h>
 #include <asm/mipsregs.h>
 
-/*
- * MIPS doesn't need any special per-pte or per-vma handling, except
- * we need to flush cache for area to be unmapped.
- */
-#define tlb_start_vma(tlb, vma)                                        \
-       do {                                                    \
-               if (!tlb->fullmm)                               \
-                       flush_cache_range(vma, vma->vm_start, vma->vm_end); \
-       }  while (0)
 #define tlb_end_vma(tlb, vma) do { } while (0)
 #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
 

diff --git a/arch/nds32/include/asm/tlb.h b/arch/nds32/include/asm/tlb.h
index b35ae5eae3ab3384cbfa7032e7a5345f351d1b36..0bf7c94823819a851c0b5be0a04b0d7521909062 100644 (file)
--- a/arch/nds32/include/asm/tlb.h
+++ b/arch/nds32/include/asm/tlb.h
@@ -4,12 +4,6 @@
 #ifndef __ASMNDS32_TLB_H
 #define __ASMNDS32_TLB_H
 
-#define tlb_start_vma(tlb,vma)                                         \
-       do {                                                            \
-               if (!tlb->fullmm)                                       \
-                       flush_cache_range(vma, vma->vm_start, vma->vm_end); \
-       } while (0)
-
 #define tlb_end_vma(tlb,vma)                           \
        do {                                            \
                if(!tlb->fullmm)                        \

diff --git a/arch/nios2/include/asm/tlb.h b/arch/nios2/include/asm/tlb.h
index d3bc648e08b5dad86e5e9c449e655fe291381c91..9b518c6d0f622efb5d5dcce3009a7a7733f2b82d 100644 (file)
--- a/arch/nios2/include/asm/tlb.h
+++ b/arch/nios2/include/asm/tlb.h
@@ -15,16 +15,6 @@
 
 extern void set_mmu_pid(unsigned long pid);
 
-/*
- * NiosII doesn't need any special per-pte or per-vma handling, except
- * we need to flush cache for the area to be unmapped.
- */
-#define tlb_start_vma(tlb, vma)                                        \
-       do {                                                    \
-               if (!tlb->fullmm)                               \
-                       flush_cache_range(vma, vma->vm_start, vma->vm_end); \
-       }  while (0)
-
 #define tlb_end_vma(tlb, vma)  do { } while (0)
 #define __tlb_remove_tlb_entry(tlb, ptep, address)     do { } while (0)
 

diff --git a/arch/parisc/include/asm/tlb.h b/arch/parisc/include/asm/tlb.h
index 0c881e74d8a62cd6a4e6082178299a118b58a5d9..b1984f9cd3af4340b33795a44065b4b6f60631a8 100644 (file)
--- a/arch/parisc/include/asm/tlb.h
+++ b/arch/parisc/include/asm/tlb.h
@@ -7,11 +7,6 @@ do {   if ((tlb)->fullmm)              \
                flush_tlb_mm((tlb)->mm);\
 } while (0)
 
-#define tlb_start_vma(tlb, vma) \
-do {   if (!(tlb)->fullmm)     \
-               flush_cache_range(vma, vma->vm_start, vma->vm_end); \
-} while (0)
-
 #define tlb_end_vma(tlb, vma)  \
 do {   if (!(tlb)->fullmm)     \
                flush_tlb_range(vma, vma->vm_start, vma->vm_end); \

diff --git a/arch/sparc/include/asm/tlb_32.h b/arch/sparc/include/asm/tlb_32.h
index 343cea19e5735b200eecb8c87c1a51ef54ae9e39..68d817273de878cc495ed053734df3b5fb0f7c56 100644 (file)
--- a/arch/sparc/include/asm/tlb_32.h
+++ b/arch/sparc/include/asm/tlb_32.h
@@ -2,11 +2,6 @@
 #ifndef _SPARC_TLB_H
 #define _SPARC_TLB_H
 
-#define tlb_start_vma(tlb, vma) \
-do {                                                           \
-       flush_cache_range(vma, vma->vm_start, vma->vm_end);     \
-} while (0)
-
 #define tlb_end_vma(tlb, vma) \
 do {                                                           \
        flush_tlb_range(vma, vma->vm_start, vma->vm_end);       \

diff --git a/arch/xtensa/include/asm/tlb.h b/arch/xtensa/include/asm/tlb.h
index 0d766f9c1083a59cd4a073cb5da0dfc640a06415..1a93e350382e71ae9835d0257e79e8d387f8f83f 100644 (file)
--- a/arch/xtensa/include/asm/tlb.h
+++ b/arch/xtensa/include/asm/tlb.h
@@ -16,19 +16,10 @@
 
 #if (DCACHE_WAY_SIZE <= PAGE_SIZE)
 
-/* Note, read http://lkml.org/lkml/2004/1/15/6 */
-
-# define tlb_start_vma(tlb,vma)                        do { } while (0)
 # define tlb_end_vma(tlb,vma)                  do { } while (0)
 
 #else
 
-# define tlb_start_vma(tlb, vma)                                             \
-       do {                                                                  \
-               if (!tlb->fullmm)                                             \
-                       flush_cache_range(vma, vma->vm_start, vma->vm_end);   \
-       } while(0)
-
 # define tlb_end_vma(tlb, vma)                                               \
        do {                                                                  \
                if (!tlb->fullmm)                                             \

diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h
index e75620e41ba4c6d434d095ee043ea7925f2744cb..f0aa53db5e60bc4870e5d600668846001bb16257 100644 (file)
--- a/include/asm-generic/tlb.h
+++ b/include/asm-generic/tlb.h
@@ -19,6 +19,7 @@
 #include <linux/swap.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
 
 #ifdef CONFIG_MMU
 
@@ -356,17 +357,19 @@ static inline unsigned long tlb_get_unmap_size(struct mmu_gather *tlb)
  * the vmas are adjusted to only cover the region to be torn down.
  */
 #ifndef tlb_start_vma
-#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_start_vma(tlb, vma)                                                \
+do {                                                                   \
+       if (!tlb->fullmm)                                               \
+               flush_cache_range(vma, vma->vm_start, vma->vm_end);     \
+} while (0)
 #endif
 
-#define __tlb_end_vma(tlb, vma)                                        \
-       do {                                                    \
-               if (!tlb->fullmm)                               \
-                       tlb_flush_mmu_tlbonly(tlb);             \
-       } while (0)
-
 #ifndef tlb_end_vma
-#define tlb_end_vma    __tlb_end_vma
+#define tlb_end_vma(tlb, vma)                                          \
+do {                                                                   \
+       if (!tlb->fullmm)                                               \
+               tlb_flush_mmu_tlbonly(tlb);                             \
+} while (0)
 #endif
 
 #ifndef __tlb_remove_tlb_entry