From: Ville Syrjälä Date: Tue, 5 Feb 2019 15:50:53 +0000 (+0200) Subject: drm/i915: Fix wm latency==0 disable on skl+ X-Git-Tag: Ubuntu-5.10.0-12.13~5868^2~11^2~20 X-Git-Url: https://git.proxmox.com/?a=commitdiff_plain;h=0aded171e20e438015a95fbfe57d679dbf228090;p=mirror_ubuntu-hirsute-kernel.git drm/i915: Fix wm latency==0 disable on skl+ When adding the early latency==0 check back I neglected to realize that we no longer have a way to return a failure from the wm computation like we had in the past (since we now calculate wms before ddb allocations). Also plane_en being false doesn't actually indicate that the level is invalid as it wil also happen when the plane is not enabled. skl_allocate_pipe_ddb() starts scanning from the maximum watermark level and it stops as soon as it finds a level that is deemed viable. The assumption being that if level n+1 is valid then level n is valid as well. Thus if we now disable any watermark level by zeroing its latency the code will think that level to be actually valid and won't confirm whether the actually enabled lower watermark level(s) actually fit into the allotted ddb space. This results in hilarious watermark values that exceed the ddb allocation of the plane. The way we must now indicate a failure is to assign an unreasoanbly big value to min_ddb_alloc which will then make skl_allocate_pipe_ddb() reject the entire level. v2: Also do the same for the lines>31 case (Matt) v3: Make 'blocks' u32 (Matt) Cc: Matt Roper Cc: Stanislav Lisovskiy Reviewed-by: Matt Roper Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20190205155053.10081-1-ville.syrjala@linux.intel.com --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ed9786241307..737005bf6816 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4319,7 +4319,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, int num_active; u64 plane_data_rate[I915_MAX_PLANES] = {}; u64 uv_plane_data_rate[I915_MAX_PLANES] = {}; - u16 blocks = 0; + u32 blocks; int level; /* Clear the partitioning for disabled planes. */ @@ -4694,8 +4694,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate, uint_fixed_16_16_t selected_result; u32 res_blocks, res_lines, min_ddb_alloc = 0; - if (latency == 0) + if (latency == 0) { + /* reject it */ + result->min_ddb_alloc = U16_MAX; return; + } /* Display WA #1141: kbl,cfl */ if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || @@ -4783,8 +4786,11 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *cstate, if (!skl_wm_has_lines(dev_priv, level)) res_lines = 0; - if (res_lines > 31) + if (res_lines > 31) { + /* reject it */ + result->min_ddb_alloc = U16_MAX; return; + } /* * If res_lines is valid, assume we can use this watermark level