From: Olivier Martin Date: Fri, 4 Jul 2014 11:20:45 +0000 (+0000) Subject: ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLib (cont) X-Git-Tag: edk2-stable201903~11371 X-Git-Url: https://git.proxmox.com/?a=commitdiff_plain;h=397bdc990b018cb2fff01413636b4a23c4b23624;p=mirror_edk2.git ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLib (cont) ... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix. The renaming did not work well with SVN. Files were missing from the initial commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15622 6f19259b-4bc3-4df7-8a09-765794883524 --- diff --git a/ArmPkg/Drivers/ArmGic/ArmGic.c b/ArmPkg/Drivers/ArmGic/ArmGic.c deleted file mode 100644 index 1717368a7e..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGic.c +++ /dev/null @@ -1,59 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include -#include - -UINTN -EFIAPI -ArmGicGetMaxNumInterrupts ( - IN INTN GicDistributorBase - ) -{ - return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1); -} - -VOID -EFIAPI -ArmGicSendSgiTo ( - IN INTN GicDistributorBase, - IN INTN TargetListFilter, - IN INTN CPUTargetList, - IN INTN SgiId - ) -{ - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId); -} - -UINTN -EFIAPI -ArmGicAcknowledgeInterrupt ( - IN UINTN GicInterruptInterfaceBase - ) -{ - // Read the Interrupt Acknowledge Register - return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); -} - -VOID -EFIAPI -ArmGicEndOfInterrupt ( - IN UINTN GicInterruptInterfaceBase, - IN UINTN Source - ) -{ - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source); -} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c new file mode 100644 index 0000000000..0fe62f2f53 --- /dev/null +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -0,0 +1,122 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include + +UINTN +EFIAPI +ArmGicGetInterfaceIdentification ( + IN INTN GicInterruptInterfaceBase + ) +{ + // Read the GIC Identification Register + return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIIDR); +} + +UINTN +EFIAPI +ArmGicGetMaxNumInterrupts ( + IN INTN GicDistributorBase + ) +{ + return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1); +} + +VOID +EFIAPI +ArmGicSendSgiTo ( + IN INTN GicDistributorBase, + IN INTN TargetListFilter, + IN INTN CPUTargetList, + IN INTN SgiId + ) +{ + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId); +} + +UINTN +EFIAPI +ArmGicAcknowledgeInterrupt ( + IN UINTN GicInterruptInterfaceBase + ) +{ + // Read the Interrupt Acknowledge Register + return MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); +} + +VOID +EFIAPI +ArmGicEndOfInterrupt ( + IN UINTN GicInterruptInterfaceBase, + IN UINTN Source + ) +{ + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source); +} + +VOID +EFIAPI +ArmGicEnableInterrupt ( + IN UINTN GicDistributorBase, + IN UINTN Source + ) +{ + UINT32 RegOffset; + UINTN RegShift; + + // Calculate enable register offset and bit position + RegOffset = Source / 32; + RegShift = Source % 32; + + // Write set-enable register + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift); +} + +VOID +EFIAPI +ArmGicDisableInterrupt ( + IN UINTN GicDistributorBase, + IN UINTN Source + ) +{ + UINT32 RegOffset; + UINTN RegShift; + + // Calculate enable register offset and bit position + RegOffset = Source / 32; + RegShift = Source % 32; + + // Write clear-enable register + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift); +} + +BOOLEAN +EFIAPI +ArmGicIsInterruptEnabled ( + IN UINTN GicDistributorBase, + IN UINTN Source + ) +{ + UINT32 RegOffset; + UINTN RegShift; + + // Calculate enable register offset and bit position + RegOffset = Source / 32; + RegShift = Source % 32; + + return ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0); +} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c deleted file mode 100644 index 55ff56e797..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicNonSec.c +++ /dev/null @@ -1,44 +0,0 @@ -/** @file -* -* Copyright (c) 2011, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include - - -VOID -EFIAPI -ArmGicEnableInterruptInterface ( - IN INTN GicInterruptInterfaceBase - ) -{ - /* - * Enable the CPU interface in Non-Secure world - * Note: The ICCICR register is banked when Security extensions are implemented - */ - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1); -} - -VOID -EFIAPI -ArmGicEnableDistributor ( - IN INTN GicDistributorBase - ) -{ - /* - * Enable GIC distributor in Non-Secure world. - * Note: The ICDDCR register is banked when Security extensions are implemented - */ - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1); -} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c new file mode 100644 index 0000000000..0bbc509550 --- /dev/null +++ b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c @@ -0,0 +1,65 @@ +/** @file +* +* Copyright (c) 2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + + +VOID +EFIAPI +ArmGicEnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + /* + * Enable the CPU interface in Non-Secure world + * Note: The ICCICR register is banked when Security extensions are implemented + */ + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1); +} + +VOID +EFIAPI +ArmGicDisableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + // Disable Gic Interface + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0); + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0); +} + +VOID +EFIAPI +ArmGicEnableDistributor ( + IN INTN GicDistributorBase + ) +{ + /* + * Enable GIC distributor in Non-Secure world. + * Note: The ICDDCR register is banked when Security extensions are implemented + */ + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1); +} + +VOID +EFIAPI +ArmGicDisableDistributor ( + IN INTN GicDistributorBase + ) +{ + // Disable Gic Distributor + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0); +} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSec.c b/ArmPkg/Drivers/ArmGic/ArmGicSec.c deleted file mode 100644 index f249eac36a..0000000000 --- a/ArmPkg/Drivers/ArmGic/ArmGicSec.c +++ /dev/null @@ -1,133 +0,0 @@ -/** @file -* -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include -#include -#include -#include - -/* - * This function configures the all interrupts to be Non-secure. - * - */ -VOID -EFIAPI -ArmGicSetupNonSecure ( - IN UINTN MpId, - IN INTN GicDistributorBase, - IN INTN GicInterruptInterfaceBase - ) -{ - UINTN InterruptId; - UINTN CachedPriorityMask; - UINTN Index; - - CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR); - - // Set priority Mask so that no interrupts get through to CPU - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0); - - InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); - - // Only try to clear valid interrupts. Ignore spurious interrupts. - while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) { - // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal - ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId); - - // Next - InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); - } - - // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt). - if (ArmPlatformIsPrimaryCore (MpId)) { - // Ensure all GIC interrupts are Non-Secure - for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) { - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff); - } - } else { - // The secondary cores only set the Non Secure bit to their banked PPIs - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); - } - - // Ensure all interrupts can get through the priority mask - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask); -} - -/* - * This function configures the interrupts set by the mask to be secure. - * - */ -VOID -EFIAPI -ArmGicSetSecureInterrupts ( - IN UINTN GicDistributorBase, - IN UINTN* GicSecureInterruptMask, - IN UINTN GicSecureInterruptMaskSize - ) -{ - UINTN Index; - UINT32 InterruptStatus; - - // We must not have more interrupts defined by the mask than the number of available interrupts - ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32)); - - // Set all the interrupts defined by the mask as Secure - for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) { - InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4)); - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index])); - } -} - -VOID -EFIAPI -ArmGicEnableInterruptInterface ( - IN INTN GicInterruptInterfaceBase - ) -{ - // Set Priority Mask to allow interrupts - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); - - // Enable CPU interface in Secure world - // Enable CPU interface in Non-secure World - // Signal Secure Interrupts to CPU using FIQ line * - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, - ARM_GIC_ICCICR_ENABLE_SECURE | - ARM_GIC_ICCICR_ENABLE_NS | - ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ); -} - -VOID -EFIAPI -ArmGicDisableInterruptInterface ( - IN INTN GicInterruptInterfaceBase - ) -{ - UINT32 ControlValue; - - // Disable CPU interface in Secure world and Non-secure World - ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR); - MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS)); -} - -VOID -EFIAPI -ArmGicEnableDistributor ( - IN INTN GicDistributorBase - ) -{ - // Turn on the GIC distributor - MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1); -} diff --git a/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c new file mode 100644 index 0000000000..f249eac36a --- /dev/null +++ b/ArmPkg/Drivers/ArmGic/ArmGicSecLib.c @@ -0,0 +1,133 @@ +/** @file +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include +#include + +/* + * This function configures the all interrupts to be Non-secure. + * + */ +VOID +EFIAPI +ArmGicSetupNonSecure ( + IN UINTN MpId, + IN INTN GicDistributorBase, + IN INTN GicInterruptInterfaceBase + ) +{ + UINTN InterruptId; + UINTN CachedPriorityMask; + UINTN Index; + + CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR); + + // Set priority Mask so that no interrupts get through to CPU + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0); + + InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); + + // Only try to clear valid interrupts. Ignore spurious interrupts. + while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) { + // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal + ArmGicEndOfInterrupt (GicInterruptInterfaceBase, InterruptId); + + // Next + InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR); + } + + // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt). + if (ArmPlatformIsPrimaryCore (MpId)) { + // Ensure all GIC interrupts are Non-Secure + for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) { + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff); + } + } else { + // The secondary cores only set the Non Secure bit to their banked PPIs + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); + } + + // Ensure all interrupts can get through the priority mask + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask); +} + +/* + * This function configures the interrupts set by the mask to be secure. + * + */ +VOID +EFIAPI +ArmGicSetSecureInterrupts ( + IN UINTN GicDistributorBase, + IN UINTN* GicSecureInterruptMask, + IN UINTN GicSecureInterruptMaskSize + ) +{ + UINTN Index; + UINT32 InterruptStatus; + + // We must not have more interrupts defined by the mask than the number of available interrupts + ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32)); + + // Set all the interrupts defined by the mask as Secure + for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) { + InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4)); + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index])); + } +} + +VOID +EFIAPI +ArmGicEnableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + // Set Priority Mask to allow interrupts + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); + + // Enable CPU interface in Secure world + // Enable CPU interface in Non-secure World + // Signal Secure Interrupts to CPU using FIQ line * + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, + ARM_GIC_ICCICR_ENABLE_SECURE | + ARM_GIC_ICCICR_ENABLE_NS | + ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ); +} + +VOID +EFIAPI +ArmGicDisableInterruptInterface ( + IN INTN GicInterruptInterfaceBase + ) +{ + UINT32 ControlValue; + + // Disable CPU interface in Secure world and Non-secure World + ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR); + MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS)); +} + +VOID +EFIAPI +ArmGicEnableDistributor ( + IN INTN GicDistributorBase + ) +{ + // Turn on the GIC distributor + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1); +}