From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Date: Mon, 17 Jan 2011 22:00:08 +0000 (+0100)
Subject: mips: Break TBs after mfc0_count
X-Git-Tag: v0.14.0-rc0~138
X-Git-Url: https://git.proxmox.com/?a=commitdiff_plain;h=55807224561b9ac278bb65960b6c12666fd30db9;p=qemu.git

mips: Break TBs after mfc0_count

Break the TB after reading the count register. This makes it
possible to take timer interrupts immediately after a read of
a possibly expired timer.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---

diff --git a/target-mips/translate.c b/target-mips/translate.c
index cce77be0d..187930e3d 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -3410,8 +3410,10 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int s
             gen_helper_mfc0_count(arg);
             if (use_icount) {
                 gen_io_end();
-                ctx->bstate = BS_STOP;
             }
+            /* Break the TB to be able to take timer interrupts immediately
+               after reading count.  */
+            ctx->bstate = BS_STOP;
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -4581,8 +4583,10 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int
             gen_helper_mfc0_count(arg);
             if (use_icount) {
                 gen_io_end();
-                ctx->bstate = BS_STOP;
             }
+            /* Break the TB to be able to take timer interrupts immediately
+               after reading count.  */
+            ctx->bstate = BS_STOP;
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */