From: Kevin Hilman Date: Thu, 4 Jun 2009 22:57:10 +0000 (-0700) Subject: OMAP: GPIO: clear/restore level/edge detect settings on mask/unmask X-Git-Tag: Ubuntu-5.10.0-12.13~31858^2~5^2~1 X-Git-Url: https://git.proxmox.com/?a=commitdiff_plain;h=55b6019ae29456e0f1e4087546bf4221c48622a0;p=mirror_ubuntu-hirsute-kernel.git OMAP: GPIO: clear/restore level/edge detect settings on mask/unmask If IRQ triggering is enabled, it can trigger a pending interrupt even for masked interrupts. Any pending GPIO interrupts can prevent the powerdomain from hitting retention. Problem found, reported and additional review and testing by Chunquiu Wang. Tested-by: Chunquiu Wang Signed-off-by: Kevin Hilman --- diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 26b387c12423..77bad14633e1 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -1189,6 +1189,7 @@ static void gpio_mask_irq(unsigned int irq) struct gpio_bank *bank = get_irq_chip_data(irq); _set_gpio_irqenable(bank, gpio, 0); + _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); } static void gpio_unmask_irq(unsigned int irq) @@ -1196,6 +1197,11 @@ static void gpio_unmask_irq(unsigned int irq) unsigned int gpio = irq - IH_GPIO_BASE; struct gpio_bank *bank = get_irq_chip_data(irq); unsigned int irq_mask = 1 << get_gpio_index(gpio); + struct irq_desc *desc = irq_to_desc(irq); + u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; + + if (trigger) + _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); /* For level-triggered GPIOs, the clearing must be done after * the HW source is cleared, thus after the handler has run */