From: Dave Airlie Date: Tue, 26 Jul 2016 07:26:29 +0000 (+1000) Subject: Backmerge tag 'v4.7' into drm-next X-Git-Tag: Ubuntu-5.2.0-15.16~8694^2~8 X-Git-Url: https://git.proxmox.com/?a=commitdiff_plain;h=5e580523d9128a4d8364fe89d36c38fc7819c8dd;p=mirror_ubuntu-eoan-kernel.git Backmerge tag 'v4.7' into drm-next Linux 4.7 As requested by Daniel Vetter as the conflicts were getting messy. --- 5e580523d9128a4d8364fe89d36c38fc7819c8dd diff --cc drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c index 9d764c4d253e,91e25f942d90..a6c9b4201e25 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c @@@ -2871,15 -2706,16 +2898,16 @@@ static int polaris10_get_evv_voltages(s } } - - PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, - VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), - "Error retrieving EVV voltage value!", - continue); - + if (atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, + VOLTAGE_TYPE_VDDC, + sclk, vv_id, &vddc) != 0) { + printk(KERN_WARNING "failed to retrieving EVV voltage!\n"); + continue; + } - /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ - PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), + /* need to make sure vddc is less than 2v or else, it could burn the ASIC. + * real voltage level in unit of 0.01mv */ + PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0), "Invalid VDDC value", result = -EINVAL;); /* the voltage should not be zero nor equal to leakage ID */ @@@ -3105,9 -2941,34 +3133,34 @@@ static int polaris10_set_private_data_b return 0; } + int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr) + { + struct phm_ppt_v1_information *table_info = + (struct phm_ppt_v1_information *)(hwmgr->pptable); + struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = + table_info->vdd_dep_on_mclk; + struct phm_ppt_v1_voltage_lookup_table *lookup_table = + table_info->vddc_lookup_table; + uint32_t i; + + if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7) { + if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000) + return 0; + + for (i = 0; i < lookup_table->count; i++) { + if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) { + dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i; + return 0; + } + } + } + return 0; + } + + int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { - struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data; struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; uint32_t temp_reg; int result; diff --cc drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h index fd38b0d7a3c2,afc3434822d1..dbc6d9bfd5af --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h @@@ -309,8 -309,13 +309,9 @@@ struct polaris10_hwmgr uint32_t up_hyst; uint32_t disable_dpm_mask; bool apply_optimized_settings; - - /* soft pptable for re-uploading into smu */ - void *soft_pp_table; - uint32_t avfs_vdroop_override_setting; bool apply_avfs_cks_off_voltage; + uint32_t frame_time_x2; }; /* To convert to Q8.8 format for firmware */ diff --cc drivers/gpu/drm/i915/intel_lrc.c index 70c699043d0e,7f2d8415ed8b..414ddda43922 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@@ -1097,6 -1103,7 +1097,7 @@@ static inline int gen8_emit_flush_coher uint32_t *const batch, uint32_t index) { - struct drm_i915_private *dev_priv = engine->dev->dev_private; ++ struct drm_i915_private *dev_priv = engine->i915; uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); /* @@@ -1267,11 -1274,13 +1268,12 @@@ static int gen9_init_indirectctx_bb(str uint32_t *offset) { int ret; - struct drm_device *dev = engine->dev; - struct drm_i915_private *dev_priv = dev->dev_private; ++ struct drm_i915_private *dev_priv = engine->i915; uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); /* WaDisableCtxRestoreArbitration:skl,bxt */ - if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) || - IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || - IS_BXT_REVID(dev, 0, BXT_REVID_A1)) ++ if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) || ++ IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ diff --cc drivers/gpu/drm/i915/intel_opregion.c index c27d5eb063d0,16e209d326b6..adca262d591a --- a/drivers/gpu/drm/i915/intel_opregion.c +++ b/drivers/gpu/drm/i915/intel_opregion.c @@@ -1072,5 -1038,16 +1072,16 @@@ intel_opregion_get_panel_type(struct dr return -ENODEV; } + /* + * FIXME On Dell XPS 13 9350 the OpRegion panel type (0) gives us + * low vswing for eDP, whereas the VBT panel type (2) gives us normal + * vswing instead. Low vswing results in some display flickers, so + * let's simply ignore the OpRegion panel type on SKL for now. + */ - if (IS_SKYLAKE(dev)) { ++ if (IS_SKYLAKE(dev_priv)) { + DRM_DEBUG_KMS("Ignoring OpRegion panel type (%d)\n", ret - 1); + return -ENODEV; + } + return ret - 1; } diff --cc drivers/gpu/drm/i915/intel_pm.c index 5a8ee0c76593,2863b92c9da6..f4f3fcc8b3be --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@@ -7021,32 -6726,9 +7021,32 @@@ static void lpt_suspend_hw(struct drm_d } } +static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, + int general_prio_credits, + int high_prio_credits) +{ + u32 misccpctl; + + /* WaTempDisableDOPClkGating:bdw */ + misccpctl = I915_READ(GEN7_MISCCPCTL); + I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); + + I915_WRITE(GEN8_L3SQCREG1, + L3_GENERAL_PRIO_CREDITS(general_prio_credits) | + L3_HIGH_PRIO_CREDITS(high_prio_credits)); + + /* + * Wait at least 100 clocks before re-enabling clock gating. + * See the definition of L3SQCREG1 in BSpec. + */ + POSTING_READ(GEN8_L3SQCREG1); + udelay(1); + I915_WRITE(GEN7_MISCCPCTL, misccpctl); +} + static void kabylake_init_clock_gating(struct drm_device *dev) { - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = dev->dev_private; gen9_init_clock_gating(dev);