From: Peter Maydell Date: Thu, 25 Oct 2018 16:41:03 +0000 (+0100) Subject: Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' into staging X-Git-Tag: v3.1.0~103 X-Git-Url: https://git.proxmox.com/?a=commitdiff_plain;h=808ebd66e467f77c0d1f8c6346235f81e9c99cf2;p=mirror_qemu.git Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' into staging First RISC-V Patch Set for the 3.1 Soft Freeze This pull request contains a handful of patches that have been floating around various trees for a while but haven't made it upstream. These patches all appear quite safe. They're all somewhat independent from each other: * One refactors our IRQ management function to allow multiple interrupts to be raised an once. This patch has no functional difference. * Cleaning up the op_helper/cpu_helper split. This patch has no functional difference. * Updates to various constants to keep them in sync with the latest ISA specification and to remove some non-standard bits that snuck in. * A fix for a memory leak in the PLIC driver. * A fix to our device tree handling to avoid provinging a NULL string. I've given this my standard test: building the port, booting a Fedora root filesytem on the latest Linux tag, and then shutting down that image. Essentially I'm just following the QEMU RISC-V wiki page's instructions. Everything looks fine here. We have a lot more outstanding patches so I'll definately be submitting another PR for the soft freeze. # gpg: Signature made Wed 17 Oct 2018 21:17:52 BST # gpg: using RSA key EF4CA1502CCBAB41 # gpg: Good signature from "Palmer Dabbelt " # gpg: aka "Palmer Dabbelt " # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/riscv/tags/riscv-for-master-3.1-sf0: RISC-V: Don't add NULL bootargs to device-tree RISC-V: Add missing free for plic_hart_config RISC-V: Update CSR and interrupt definitions RISC-V: Move non-ops from op_helper to cpu_helper RISC-V: Allow setting and clearing multiple irqs Signed-off-by: Peter Maydell --- 808ebd66e467f77c0d1f8c6346235f81e9c99cf2