From: Stefan Hajnoczi <stefanha@redhat.com>
Date: Wed, 22 Nov 2023 14:39:23 +0000 (-0500)
Subject: Merge tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu into... 
X-Git-Tag: v8.2.0~29
X-Git-Url: https://git.proxmox.com/?a=commitdiff_plain;h=b93c4313f2f40897bdafba15620c8fef6c20e721;hp=-c;p=mirror_qemu.git

Merge tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu into staging

Fourth RISC-V PR for 8.2

This is a few bug fixes for the 8.2 release

* Add Zicboz block size to hwprobe
* Creat the virt machine FDT before machine init is complete
* Don't verify ISA compatibility for zicntr and zihpm
* Fix SiFive E CLINT clock frequency
* Fix invalid exception on MMU translation stage
* Fix mxr bit behavior

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# gpg: Signature made Wed 22 Nov 2023 00:37:15 EST
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20231122' of https://github.com/alistair23/qemu:
  target/riscv/cpu_helper.c: Fix mxr bit behavior
  target/riscv/cpu_helper.c: Invalid exception on MMU translation stage
  riscv: Fix SiFive E CLINT clock frequency
  target/riscv: don't verify ISA compatibility for zicntr and zihpm
  hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt()
  linux-user/riscv: Add Zicboz block size to hwprobe

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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b93c4313f2f40897bdafba15620c8fef6c20e721