From: Liming Gao <liming.gao@intel.com>
Date: Wed, 19 Nov 2014 02:30:21 +0000 (+0000)
Subject: MdeModulePkg BaseSerialPortLib16550: Correct MemoryLimit and MemoryBase offset.
X-Git-Tag: edk2-stable201903~10608
X-Git-Url: https://git.proxmox.com/?a=commitdiff_plain;h=c9e0bba3855c18728199b99dada6d03102ca331c;p=mirror_edk2.git

MdeModulePkg BaseSerialPortLib16550: Correct MemoryLimit and MemoryBase offset.

Their offset in PCI-to-PCI Bridge Configuration Space.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16402 6f19259b-4bc3-4df7-8a09-765794883524
---

diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
index d21c00c5a4..0ade9b2311 100644
--- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
+++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
@@ -244,8 +244,8 @@ GetSerialRegisterBase (
     // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
     //
     if (PcdGetBool (PcdSerialUseMmio)) {
-      MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, MemoryLimit)) & 0xfff0;
-      MemoryBase  = PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, MemoryBase))  & 0xfff0;
+      MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0;
+      MemoryBase  = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase))  & 0xfff0;
 
       //
       // If PCI Bridge MMIO window is disabled, then return 0
@@ -263,17 +263,17 @@ GetSerialRegisterBase (
       ParentMemoryBase  = MemoryBase;
       ParentMemoryLimit = MemoryLimit;
     } else {
-      IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoLimit));
+      IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
       if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
         IoLimit = IoLimit >> 4;
       } else {
-        IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoLimitUpper16)) << 4) | (IoLimit >> 4);
+        IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);
       }
-      IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoBase));
+      IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
       if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
         IoBase = IoBase >> 4;
       } else {
-        IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoBaseUpper16)) << 4) | (IoBase >> 4);
+        IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
       }
       
       //