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Merge tag 'pull-tcg-20231114' of https://gitlab.com/rth7680/qemu into staging
[mirror_qemu.git] / target / riscv / cpu.h
2023-11-10 Stefan HajnocziMerge tag 'xen-virtio-fix-1-tag' of https://gitlab...
2023-11-09 Stefan HajnocziMerge tag 'for-upstream' of https://repo.or.cz/qemu...
2023-11-08 Stefan HajnocziMerge tag 'pull-ppc-20231107' of https://gitlab.com...
2023-11-08 Stefan HajnocziMerge tag 'misc-fixes-pull-request' of https://gitlab...
2023-11-08 Stefan HajnocziMerge tag 'pull-request-2023-11-07' of https://gitlab...
2023-11-08 Stefan HajnocziMerge tag 'misc-cpus-20231107' of https://github.com...
2023-11-07 Philippe Mathieu... target: Move ArchCPUClass definition to 'cpu.h'
2023-11-07 Philippe Mathieu... target/riscv: Move TYPE_RISCV_CPU_BASE definition to...
2023-11-07 Philippe Mathieu... target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'
2023-11-07 Philippe Mathieu... target: Unify QOM style
2023-11-07 Stefan HajnocziMerge tag 'for_upstream' of https://git.kernel.org...
2023-11-07 Stefan HajnocziMerge tag 'pull-pa-20231106' of https://gitlab.com...
2023-11-07 Stefan HajnocziMerge tag 'pull-riscv-to-apply-20231107' of https:...
2023-11-07 Daniel Henrique... target/riscv: add riscv_cpu_accelerator_compatible()
2023-11-07 Daniel Henrique... target/riscv/tcg: add tcg_cpu_finalize_features()
2023-11-07 Rajnesh Kanwaltarget/riscv: Add HS-mode virtual interrupt and IRQ...
2023-11-07 Rajnesh Kanwaltarget/riscv: Add M-mode virtual interrupt and IRQ...
2023-11-07 Rajnesh Kanwaltarget/riscv: Split interrupt logic from riscv_cpu_upda...
2023-10-16 Stefan HajnocziMerge tag 'python-pull-request' of https://gitlab.com...
2023-10-16 Stefan HajnocziMerge tag 'pull-request-2023-10-12' of https://gitlab...
2023-10-16 Stefan HajnocziMerge tag 'for-upstream' of https://repo.or.cz/qemu...
2023-10-16 Stefan HajnocziMerge tag 'pull-shadow-2023-10-12' of https://repo...
2023-10-16 Stefan HajnocziMerge tag 'mem-2023-10-12' of https://github.com/davidh...
2023-10-12 Stefan HajnocziMerge tag 'pull-riscv-to-apply-20231012-1' of https...
2023-10-12 Daniel Henrique... target/riscv: deprecate capital 'Z' CPU properties
2023-10-12 Daniel Henrique... target/riscv: add riscv_cpu_get_name()
2023-10-12 Daniel Henrique... target/riscv/cpu: move priv spec functions to tcg-cpu.c
2023-10-12 Daniel Henrique... target/riscv/cpu.c: export isa_edata_arr[]
2023-10-12 Daniel Henrique... target/riscv/tcg: move riscv_cpu_add_misa_properties...
2023-10-12 Daniel Henrique... target/riscv/tcg: introduce tcg_cpu_instance_init()
2023-10-12 Daniel Henrique... target/riscv/cpu.c: export set_misa()
2023-10-12 Daniel Henrique... target/riscv/kvm: do not use riscv_cpu_add_misa_propert...
2023-10-12 Daniel Henrique... target/riscv: make riscv_add_satp_mode_properties(...
2023-10-12 Daniel Henrique... target/riscv: move riscv_cpu_add_kvm_properties() to...
2023-10-12 Daniel Henrique... target/riscv: move riscv_tcg_ops to tcg-cpu.c
2023-10-12 Daniel Henrique... target/riscv: move riscv_cpu_validate_set_extensions...
2023-10-12 Daniel Henrique... target/riscv: introduce TCG AccelCPUClass
2023-10-12 Daniel Henrique... target/riscv: make CPUCFG() macro public
2023-10-05 Stefan HajnocziMerge tag 'for_upstream' of https://git.kernel.org...
2023-10-05 Stefan HajnocziMerge tag 'pull-tcg-20231004' of https://gitlab.com...
2023-10-03 Richard Hendersonaccel/tcg: Move CPUNegativeOffsetState into CPUState
2023-09-21 Stefan HajnocziMerge tag 'pull-block-2023-09-01' of https://gitlab...
2023-09-11 Stefan HajnocziMerge tag 'for-upstream' of https://repo.or.cz/qemu...
2023-09-11 Stefan HajnocziMerge tag 'pull-target-arm-20230908' of https://git...
2023-09-08 Stefan HajnocziMerge tag 'pull-trivial-patches' of https://gitlab...
2023-09-08 Michael Tokarevriscv: spelling fixes
2023-07-24 Peter MaydellMerge tag 'pull-qapi-2023-07-10' of https://repo.or...
2023-07-11 Richard HendersonMerge tag 'for_upstream' of https://git.kernel.org...
2023-07-11 Richard HendersonMerge tag 'mips-20230710' of https://github.com/philmd...
2023-07-10 Richard HendersonMerge tag 'qga-pull-2023-07-10' of https://github.com...
2023-07-10 Richard HendersonMerge tag 'pull-riscv-to-apply-20230710-1' of https...
2023-07-10 Daniel Henrique... target/riscv/cpu: add misa_ext_info_arr[]
2023-07-10 Weiwei Litarget/riscv: Add additional xlen for address when...
2023-06-30 Richard HendersonMerge tag 'pull-request-2023-06-29' of https://gitlab...
2023-06-29 Richard HendersonMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2023-06-29 Richard HendersonMerge tag 'accel-20230628' of https://github.com/philmd...
2023-06-28 Richard HendersonMerge tag 'for-upstream' of https://repo.or.cz/qemu...
2023-06-28 Richard HendersonMerge tag 'for_upstream' of https://git.kernel.org...
2023-06-28 Philippe Mathieu... target/riscv: Restrict KVM-specific fields from ArchCPU
2023-06-26 Richard HendersonMerge tag 'pull-tcg-20230626' of https://gitlab.com...
2023-06-26 Anton Johanssontarget: Widen pc/cs_base in cpu_get_tb_cpu_state
2023-06-21 Richard HendersonMerge tag 'seabios-hppa-v7-pull-request' of https:...
2023-06-14 Richard HendersonMerge tag 'pull-riscv-to-apply-20230614' of https:...
2023-06-13 Weiwei Litarget/riscv: Split RISCVCPUConfig declarations from...
2023-06-13 Daniel Henrique... target/riscv: rework write_misa()
2023-06-13 Daniel Henrique... target/riscv: add PRIV_VERSION_LATEST
2023-05-17 Richard HendersonMerge tag 'linux-user-for-8.1-pull-request' of https...
2023-05-13 Richard HendersonMerge tag 'or1k-pull-request-20230513' of https://githu...
2023-05-05 Richard HendersonMerge tag 'pw-pull-request' of https://gitlab.com/marca...
2023-05-05 Richard HendersonMerge tag 'migration-20230505-pull-request' of https...
2023-05-05 Richard HendersonMerge tag 'pull-riscv-to-apply-20230505-1' of https...
2023-05-05 Daniel Henrique... target/riscv: add CPU QOM header
2023-05-05 Richard Hendersontarget/riscv: Introduce mmuidx_2stage
2023-05-05 Richard Hendersontarget/riscv: Handle HLV, HSV via helpers
2023-05-05 Fei Wutarget/riscv: Reduce overhead of MSTATUS_SUM change
2023-05-05 Fei Wutarget/riscv: Separate priv from mmu_idx
2023-05-05 LIU Zhiweitarget/riscv: Add a tb flags field for vstart
2023-05-05 Richard Hendersontarget/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
2023-05-05 LIU Zhiweitarget/riscv: Encode the FS and VS on a normal way...
2023-05-05 LIU Zhiweitarget/riscv: Add a general status enum for extensions
2023-05-05 LIU Zhiweitarget/riscv: Extract virt enabled state from tb flags
2023-05-05 Weiwei Litarget/riscv: Use PRV_RESERVED instead of PRV_H
2023-05-05 Daniel Henrique... target/riscv/cpu.c: redesign register_cpu_props()
2023-05-05 Daniel Henrique... target/riscv: add RVG and remove cpu->cfg.ext_g
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_v
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_j
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_h
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_u
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_s
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_m
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_e
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_i
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_f
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_d
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_c
2023-05-05 Daniel Henrique... target/riscv: remove cpu->cfg.ext_a
2023-05-05 Weiwei Litarget/riscv: Fix lines with over 80 characters
2023-05-05 Weiwei Litarget/riscv: Fix format for comments
2023-05-05 Weiwei Litarget/riscv: Remove riscv_cpu_virt_enabled()
2023-05-05 LIU Zhiweitarget/riscv: Convert env->virt to a bool env->virt_enabled
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