Hawking Zhang [Sat, 12 Dec 2020 14:16:58 +0000 (22:16 +0800)]
drm/amdgpu: drop ih reroute function from psp v11
For all the ASICs that integrate psp v11, vega20
doesn't support ih reroute. arcturus and later will
allow kernel driver to program ih_cfg_index/data
through mmio directly. navi1x and onwards will only
support grb_ih_set command in sriov configuration.
psp_v11_0_reroute_ih is not needed any more.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 16:23:16 +0000 (00:23 +0800)]
drm/amdgpu: drop IH_CHICKEN programming from vega10 ih block
except for RENOIR, it is not correct to have
IH_CHICKEN programming in vega10 ih block.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 16:04:36 +0000 (00:04 +0800)]
drm/amdgpu: correct ih_chicken programming for vega10/vega20 ih blocks
IH_CHICKEN.MC_SPACE_FBPA_ENABLE field is only
valid when IH_RB_CNTL.MC_SPACE is programed to 0x3,
frame buffer physical address. For both bus address
and gpu virtual address, don't program MC_SPACE_FBPA_ENABLE
field
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 9 Dec 2020 05:49:01 +0000 (13:49 +0800)]
drm/amdgpu: retire the vega20 code path from navi10 ih block
already switched to vega20 ih block for vega20
and arcturus. no need to add vega20 support in
navi10 ih block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 15:36:57 +0000 (23:36 +0800)]
drm/amdgpu: switch to vega20 ih block for vega20/arcturus
replace navi10 ih block with vega20 ih block for
vega20 and arcturus
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 9 Dec 2020 05:47:20 +0000 (13:47 +0800)]
drm/amdgpu: reroute vmc/utcl2 interrupts to ih ring 1 for arcturus
in case page faults overwhlem the interrupt handlers
and the driver lost the valuable interrupt information
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 18 Dec 2020 13:48:59 +0000 (21:48 +0800)]
drm/amdgpu: create vega20 ih blocks
vega20 ih blocks will be used for vega20/arcturus
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 8 Dec 2020 09:22:30 +0000 (17:22 +0800)]
drm/amdgpu: add osssys v4_2 ip headers (v2)
v1: add osssys v4_2 register offset and shift masks
header files. vega20 and arcturus will refer to
these ip headers. (Hawking)
v2: clean up osssys v4_2 registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Hawking Zhang [Wed, 25 Nov 2020 07:29:42 +0000 (15:29 +0800)]
drm/amdgpu: switch to common decode iv helper
The iv format is the same for all the soc15 adpater
and onwards and can share a common function to
decode iv.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 25 Nov 2020 07:25:51 +0000 (15:25 +0800)]
drm/amdgpu: add a helper function to decode iv
since from soc15, all the chips share the same
iv format. create a common helper to decode iv
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:30:12 +0000 (23:30 +0800)]
drm/amdgpu: use cached ih rb control reg offsets for navi10
all the ih rb control register offsets are cached
at the beginning of navi10 ih_sw_init.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 9 Dec 2020 05:36:32 +0000 (13:36 +0800)]
drm/amdgpu: switch to ih_enable_ring for navi10
use navi10_ih_enable_ring to enable all the
available ring buffers for navi1x and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:23:16 +0000 (23:23 +0800)]
drm/amdgpu: switch to ih_toggle_interrupts for navi10
replace ih_enable_interrupts and ih_disable_interrupts
with ih_toggle_interrupts
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:20:55 +0000 (23:20 +0800)]
drm/amdgpu: switch to ih_init_register_offset for navi10
Initialize ih control registers offset through helper
function navi10_ih_init_register_offset.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:19:03 +0000 (23:19 +0800)]
drm/amdgpu: add helper to toggle ih ring interrupts for navi10
navi10_ih_toggle_ring_interrupts will be used to
enable/disable an ih ring interrupts for navi1x
and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:17:13 +0000 (23:17 +0800)]
drm/amdgpu: add helper to enable an ih ring for navi10
navi10_ih_enable_ring will be used to enable an
ih ring for navi1x and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:15:32 +0000 (23:15 +0800)]
drm/amdgpu: add helper to init ih ring regs for navi10
navi10_ih_init_register_offset will be used to init
register offset for all the available ih rings
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 14:49:40 +0000 (22:49 +0800)]
drm/amdgpu: correct ih cg programming for vega10 ih block
vega10/12 and RAVEN don't support soft override
ih_buffer_mem_clk.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:13:12 +0000 (23:13 +0800)]
drm/amdgpu: use cached ih rb control reg offsets for vega10
all the ih rb control register offsets are cached
at the beginning of ih_sw_init.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 8 Dec 2020 14:10:47 +0000 (22:10 +0800)]
drm/amdgpu: switch to ih_enable_ring for vega10
use vega10_ih_enable_ring to enable all the
available ring buffers for vega10/12, RAVEN
series and RENOIR APUs
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:03:32 +0000 (23:03 +0800)]
drm/amdgpu: switch to ih_toggle_interrupts for vega10
replace ih_enable_interrupts and ih_disable_interrupts
with ih_toggle_interrupts
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:01:02 +0000 (23:01 +0800)]
drm/amdgpu: switch to ih_init_register_offset for vega10
Initialize ih control registers offset through helper
function vega10_ih_init_register_offset.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 14:54:47 +0000 (22:54 +0800)]
drm/amdgpu: add helper to toggle ih ring interrupts for vega10
vega10_ih_toggle_ring_interrupts will be used to
enable/disable an ih ring interrupts for vega10/12,
RAVEN series and RENOIR APUs
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 14:53:17 +0000 (22:53 +0800)]
drm/amdgpu: add helper to enable an ih ring for vega10
vega10_ih_enable_ring will be used to enable an
ih ring for vega10/12, RAVEN series and RENOIR.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 14:44:40 +0000 (22:44 +0800)]
drm/amdgpu: add helper to init ih ring regs for vega10
vega10_ih_init_register_offset will be used to init
register offset for all the available ih rings
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 14:36:46 +0000 (22:36 +0800)]
drm/amdgpu: add amdgpu_ih_regs structure
amdgpu_ih_regs holds all the registers for
an ih ring
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stylon Wang [Tue, 10 Nov 2020 07:40:06 +0000 (15:40 +0800)]
drm/amd/display: Fix memory leaks in S3 resume
EDID parsing in S3 resume pushes new display modes
to probed_modes list but doesn't consolidate to actual
mode list. This creates a race condition when
amdgpu_dm_connector_ddc_get_modes() re-initializes the
list head without walking the list and results in memory leak.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=209987 Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Alex Deucher [Thu, 17 Dec 2020 17:11:36 +0000 (12:11 -0500)]
drm/amdgpu: only set DP subconnector type on DP and eDP connectors
Fixes a crash in drm_object_property_set_value() because the property
is not set for internal DP ports that connect to a bridge chips
(e.g., DP to VGA or DP to LVDS).
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210739 Fixes: 65bf2cf95d3ade ("drm/amdgpu: utilize subconnector property for DP through atombios") Tested-By: Kris Karas <bugs-a17@moonlit-rail.com> Cc: Oleg Vasilev <oleg.vasilev@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 5.10.x
Jake Wang [Fri, 11 Dec 2020 21:53:57 +0000 (16:53 -0500)]
drm/amd/display: always program DPPDTO unless not safe to lower
[Why]
We defer clock updates to after pipes have been programmed. In
some instances we use DPPCLK that have been previously set to be
"unused". This results in a brief window of time where underflow
could occur.
[How]
During prepare bandwidth allow rn_update_clocks_update_dpp_dto
to check each instance and compare previous clock to new clock.
If new clock is higher than previous clock, program DPPDTO.
Signed-off-by: Jake Wang <haonan.wang2@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Fri, 11 Dec 2020 20:34:30 +0000 (15:34 -0500)]
drm/amd/display: [FW Promotion] Release 0.0.47
- restore lvtma_pwrseq_delay2 from vbios integrated info table
- restore MVID/NVID after power up.
- Enable timer wake up mask when enable timer interrupt.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sung Lee [Wed, 9 Dec 2020 19:58:59 +0000 (14:58 -0500)]
drm/amd/display: Acquire DSC during split stream for ODM only if top_pipe
[WHY]
DSC should only be acquired per OPP. Therefore, DSC should only
be acquired for the top_pipe when ODM is enabled.
Not doing this check may lead to acquiring more DSC's than needed
when doing MPO + ODM Combine.
[HOW]
Only acquire DSC if pipe is top_pipe.
Signed-off-by: Sung Lee <sung.lee@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Wed, 9 Dec 2020 21:56:51 +0000 (16:56 -0500)]
drm/amd/display: change SMU repsonse timeout to 2s.
[Why]
there is some garbage showing up during reboot test.
Reason:
SMU might handle display driver msg defered and driver will send
next msg to SMU after 10ms timeout, once SMU FW handle previous msg,
parameters are changed to next one, which result in a wrong value be programmed.
[How]
Extend timeout to 2s so SMU will have enough time to handle driver msg.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Tsai [Thu, 3 Dec 2020 02:47:11 +0000 (10:47 +0800)]
drm/amd/display: Modify the hdcp device count check condition
[why]
Some MST display may not report the internal panel to DEVICE_COUNT,
that makes the check condition always failed.
[how]
To update this condition with the reported device count + 1
(because the immediate repeater's internal panel is possibly
not included in DEVICE_COUNT)
Signed-off-by: Martin Tsai <martin.tsai@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wesley Chalmers [Mon, 7 Dec 2020 16:46:08 +0000 (11:46 -0500)]
drm/amd/display: Interfaces for hubp blank and soft reset
[WHY]
HUBP blanking sequence on DCN30 requires us to check if HUBP is in blank
and also toggle HUBP_DISABLE, which should instead be called
HUBP_SOFT_RESET for what it does in HW.
Qingqing Zhuo [Fri, 4 Dec 2020 15:55:13 +0000 (10:55 -0500)]
drm/amd/display: handler not correctly checked at remove_irq_handler
[why]
handler is supposedly passed in as a function pointer;
however, the entire struct amdgpu_dm_irq_handler_data
gets from the list is used to check match.
[how]
use the interrupt_handler within amdgpu_dm_irq_handler_data
for checking match.
Hawking Zhang [Sat, 21 Nov 2020 13:01:47 +0000 (21:01 +0800)]
drm/amdgpu: check number of gfx ring before init cp gfx
Check number of gfx ring, rather than asic type,
before cp gfx engine initialization so driver just
need to make sure number of gfx ring is initialized
correctly in gfx early_init phase. No need to add
additional asic type check everywhere when there is
new asic with gfx pipe removed.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 15 Dec 2020 17:07:55 +0000 (12:07 -0500)]
drm/amdgpu/disply: fix documentation warnings in display manager
Add documentation for crc window.
Fixes: c920888c604d ("drm/amd/display: Expose new CRC window property") Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Wayne Lin <Wayne.Lin@amd.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
Rodrigo Siqueira [Tue, 15 Dec 2020 15:33:34 +0000 (10:33 -0500)]
drm/amd/display: Add get_dig_frontend implementation for DCEx
Some old ASICs might not implement/require get_dig_frontend helper; in
this scenario, we can have a NULL pointer exception when we try to call
it inside vbios disable operation. For example, this situation might
happen when using Polaris12 with an eDP panel. This commit avoids this
situation by adding a specific get_dig_frontend implementation for DCEx.
Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Chiawen Huang <chiawen.huang@amd.com> Reported-and-tested-by: Borislav Petkov <bp@suse.de> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Tom Rix [Tue, 15 Dec 2020 14:42:23 +0000 (06:42 -0800)]
drm/radeon: remove h from printk format specifier
See Documentation/core-api/printk-formats.rst.
h should no longer be used in the format specifier for printk.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom Rix [Tue, 15 Dec 2020 14:38:35 +0000 (06:38 -0800)]
drm/amdgpu: remove h from printk format specifier
See Documentation/core-api/printk-formats.rst.
h should no longer be used in the format specifier for printk.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiange Zhao [Wed, 25 Nov 2020 13:56:05 +0000 (21:56 +0800)]
drm/amdgpu/SRIOV: Extend VF reset request wait period
In Virtualization case, when one VF is sending too many
FLR requests, hypervisor would stop responding to this
VF's request for a long period of time. This is called
event guard. During this period of cooling time, guest
driver should wait instead of doing other things. After
this period of time, guest driver would resume reset
process and return to normal.
Currently, guest driver would wait 12 seconds and return fail
if it doesn't get response from host.
Solution: extend this waiting time in guest driver and poll
response periodically. Poll happens every 6 seconds and it will
last for 60 seconds.
v2: change the max repetition times from number to macro.
Souptick Joarder [Fri, 11 Dec 2020 19:32:36 +0000 (01:02 +0530)]
drm/amd/display: Fixed kernel test robot warning
Kernel test robot throws below warning ->
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5:
warning: no previous prototype for 'amdgpu_dm_crtc_atomic_set_property'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5:
warning: no previous prototype for function
'amdgpu_dm_crtc_atomic_set_property' [-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5373:5:
warning: no previous prototype for 'amdgpu_dm_crtc_atomic_get_property'
[-Wmissing-prototypes]
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5373:5:
warning: no previous prototype for function
'amdgpu_dm_crtc_atomic_get_property' [-Wmissing-prototypes]
As these functions are only used inside amdgpu_dm.c, these can be
made static.
Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sun, 6 Dec 2020 18:57:54 +0000 (13:57 -0500)]
drm/amd/display: [FW Promotion] Release 0.0.46
- Add new aux_channel_type
- Changed port_index to instance in dmub_cmd_dp_aux_control_data
- Change aux_return_code_type to sync up with driver
- param for ramping abm based on backlight level
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The OGAM LUT precision was accumulating too much error
in the higher end.
[How]
Instead of calculating all points of the LUT in relation
to the previous ones, perform a full calculation in one
of the intermediate segments to stop error propagation.
Signed-off-by: Felipe Clark <Felipe.Clark@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Leung [Wed, 2 Dec 2020 20:10:12 +0000 (15:10 -0500)]
drm/amd/display: delay fp2 programming until vactive before lock
[Why]
race condition of programming FP2 wrt pipe locking
and vactive state can cause underflow/black screen
[How]
Enforce the FP2 is only programmed during vactive,
and unlock pipe soon afterwards.
Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add DP info frame update for dcn30
[Why]
We are missing the DP info frame update on dcn30, and this will
lead to DP SDPs not being sent;
[How]
Add the DP info frame update for dcn30;
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Tue, 24 Nov 2020 11:57:03 +0000 (19:57 +0800)]
drm/amd/display: Fix to be able to stop crc calculation
[Why]
Find out when we try to disable CRC calculation,
crc generation is still enabled. Main reason is
that dc_stream_configure_crc() will never get
called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE.
[How]
Add checking condition that when source is
AMDGPU_DM_PIPE_CRC_SOURCE_NONE, we should also call
dc_stream_configure_crc() to disable crc calculation.
Also, clean up crc window when disable crc calculation.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Tue, 1 Dec 2020 16:25:50 +0000 (11:25 -0500)]
drm/amd/display: HP Reverb G2 VR fails to light up
[Why]
Many VR headsets require a HSYNC width of 4, but DCN
has default minimum of 8.
[How]
Change the arbitrary minimum HSYNC width to 4 to match
DCN20.
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Lu [Tue, 24 Nov 2020 15:06:04 +0000 (10:06 -0500)]
drm/amd/display: Change pstate expected timeout warning to 180us on linux
[Why]
There is a warning that triggers when pstate takes too long.
Pstate can take up to ~200us on Linux without hanging but
it is currently set to 40us.
[How]
Change the timeout for the warning to be 180us on Linux.
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stanley.Yang [Fri, 11 Dec 2020 12:59:47 +0000 (20:59 +0800)]
drm/amdgpu: skip load smu and sdma microcode on sriov for SIENNA_CICHLID
skip load smu and sdma fw on sriov due to sos,
ta and asd fw have been skipped for SIENNA_CICHLID.
V2:
move asic check into smu11
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 15 Dec 2020 16:32:20 +0000 (11:32 -0500)]
drm/amdgpu: add judgement for suspend/resume sequence
S0ix only makes sense on APUs since they are part of the platform, so
only when the ASIC is APU should set amdgpu_acpi_is_s0ix_supported flag
to deal with the related situation.
Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaomeng Hou [Thu, 10 Dec 2020 12:18:23 +0000 (20:18 +0800)]
drm/amdgpu/sdma5.2: soft reset sdma blocks before setup and start sdma
Without doing the soft reset, register mmSDMA0_GFX_RB_WPTR's value could not be
reset to 0 when sdma block resumes. That would cause the ring buffer's read and
write pointers not equal and ring test fail. So add the soft reset step.
Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 10 Dec 2020 08:36:28 +0000 (16:36 +0800)]
drm/amd/pm: add deep sleep control for uclk and fclk
These are supported by Sienna Cichlid and should be
taken into consideration during DS control.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 10 Dec 2020 04:42:24 +0000 (12:42 +0800)]
drm/amd/pm: update the data strucutre for SMU metrics exchange
This is needed for Sienna Cichlid.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 10 Dec 2020 04:03:50 +0000 (12:03 +0800)]
drm/amd/pm: correct the data structure for activity monitor coeff exchange
This is needed for Sienna Cichlid.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 9 Dec 2020 06:30:29 +0000 (14:30 +0800)]
drm/amd/pm: fulfill the sienna cichlid UMD PSTATE profiling clocks
Fulfill the UMD PSTATE profiling clocks of sienna cichlid.
Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaomeng Hou [Tue, 1 Dec 2020 10:33:33 +0000 (18:33 +0800)]
drm/amd/pm: inform SMU RLC status thus enable/disable DPM feature for vangogh
RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFW is
unaware of RLC being halted and will continue sending messages, which would
eventually cause an ACPI hang. Use the system_feature_control interface to
notify SMU the status of RLC (Normal/OFF) thus enable/disable DPM feature.
Evan Quan [Wed, 9 Dec 2020 08:34:22 +0000 (16:34 +0800)]
drm/amd/pm: typo fix (CUSTOM -> COMPUTE)
The "COMPUTE" was wrongly spelled as "CUSTOM".
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / mirror_ubuntu-kernels.git / log