Evan Quan [Tue, 7 Jul 2020 03:10:39 +0000 (11:10 +0800)]
drm/amd/powerplay: move dpm feature enablement checking to smu_cmn.c
Considering it is shared by all ASICs and smu_cmn.c should be
the right place.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 7 Jul 2020 02:18:02 +0000 (10:18 +0800)]
drm/amd/powerplay: move dpm feature support checking to smu_cmn.c
Considering it is shared by all ASICs and smu_cmn.c should be
the right place.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 7 Jul 2020 02:24:31 +0000 (10:24 +0800)]
drm/amd/powerplay: move clock dpm enablement check to smu_v11/v12
As those APIs of smu_v11/v12 are more widely called. And they
need this check also.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 6 Jul 2020 08:18:57 +0000 (16:18 +0800)]
drm/amd/powerplay: drop unused code
Those code were obsoleted by new common API
smu_cmn_to_asic_specific_index().
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 6 Jul 2020 08:11:31 +0000 (16:11 +0800)]
drm/amd/powerplay: unify swSMU index to asic specific index mapping
By this we can drop redundant code.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 6 Jul 2020 03:03:00 +0000 (11:03 +0800)]
drm/amd/powerplay: widely share the API for data table retrieving
Considering the data table retrieving can be more widely shared,
amdgpu_atombios.c is the right place.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 15 Jul 2020 06:01:29 +0000 (14:01 +0800)]
drm/amd/powerplay: suppress compile error around BUG_ON
To suppress the compile error below for "ARCH=arc".
drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c: In function 'arcturus_fill_eeprom_i2c_req':
>> arch/arc/include/asm/bug.h:22:2: error: implicit declaration of function 'pr_warn'; did you mean 'pci_warn'? [-Werror=implicit-function-declaration]
22 | pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
| ^~~~~~~
include/asm-generic/bug.h:62:57: note: in expansion of macro 'BUG'
62 | #define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while (0)
| ^~~
drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2157:2: note: in expansion of macro 'BUG_ON'
2157 | BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 21 Jul 2020 19:31:52 +0000 (15:31 -0400)]
drm/amdgpu/smu11: drop code chuck that got accidently re-added
Seems to be due to a bad merge. Code was originally added in
commit 5aaa8fff3aa950 ("drm/amd/powerplay: unload mp1 for Arcturus RAS baco reset")
but later removed in commit 7f70443fd83407 ("drm/amdgpu: set mp1 state before reload").
but is back again.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Tue, 19 May 2020 20:48:43 +0000 (16:48 -0400)]
drm/amd/amdkfd: Fix large framesize for kfd_smi_ev_read()
The buffer allocated is of 1024 bytes. Allocate this from
heap instead of stack.
Also remove check for stack size since we're allocating from heap
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Amber Lin [Mon, 20 Apr 2020 23:42:46 +0000 (19:42 -0400)]
include/uapi/linux: Update KFD ioctl version
Bump KFD ioctl after adding SMI events support
Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Amber Lin [Wed, 13 May 2020 12:19:29 +0000 (08:19 -0400)]
drm/amdkfd: Provide SMI events watch
When the compute is malfunctioning or performance drops, the system admin
will use SMI (System Management Interface) tool to monitor/diagnostic what
went wrong. This patch provides an event watch interface for the user
space to register devices and subscribe events they are interested. After
registered, the user can use annoymous file descriptor's poll function
with wait-time specified and wait for events to happen. Once an event
happens, the user can use read() to retrieve information related to the
event.
VM fault event is done in this patch.
v2: - remove UNREGISTER and add event ENABLE/DISABLE
- correct kfifo usage
- move event message API to kfd_ioctl.h
v3: send the event msg in text than in binary
v4: support multiple clients
v5: move events enablement from ioctl to fd write
v6: sparse fix
Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: set VCN1 pg only for sienna_cichlid
navy_flounder has one VCN instance, and the work around
is to avoid smu reponse error when setting VCN1 pg for
the chip. It is preferred VCN0 and VCN1 are separated
for the pg setting so better power efficiency can be
achieved.
drm/amdgpu/powerplay: add smu support for navy_flounder
Now navy_flounder will reuse the smu11 driver_if header and ppt
functions for sienna_cichlid. Later navy_flounder can maintain
its own version if the compatibility is broken.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sat, 12 Oct 2019 11:55:48 +0000 (19:55 +0800)]
drm/amdgpu: expand to add multiple trap event irq id
Sienna_cichlid has four sdma instances, but other chips don't.
So we need expand to add multiple trap event irq id in sdma
v5.2.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Mon, 29 Jun 2020 01:55:26 +0000 (09:55 +0800)]
drm/amd/sriov add mmsch_v3 interface
For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch
to set the World Switch for MM appropriately. This patch add
the interface for mmsch_v3.0.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Wed, 24 Jun 2020 02:19:20 +0000 (10:19 +0800)]
drm/amdgpu: optimize rlcg write for gfx_v10
For gfx10 boards, except for nv12, other boards take mmio write
rather than rlcg write
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Tue, 23 Jun 2020 11:36:24 +0000 (19:36 +0800)]
drm/amd/sriov skip jped ip block and close pgcg flags
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 08:06:55 +0000 (16:06 +0800)]
drm/amd/powerplay: drop unused code around thermal range setting
Leftover of previous cleanups.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 07:59:03 +0000 (15:59 +0800)]
drm/amd/powerplay: maximum the code sharing on thermal irq setting
Put the common code in smu_v11_0.c instead of having one copy each.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 07:38:53 +0000 (15:38 +0800)]
drm/amd/powerplay: sort the call flow on temperature ranges retrieving
This can help to maintain clear code layer.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 07:13:02 +0000 (15:13 +0800)]
drm/amd/powerplay: cache the software_shutdown_temp
As it's needed in the succeeding thermal irq setting.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 06:56:34 +0000 (14:56 +0800)]
drm/amd/powerplay: correct Sienna Cichlid temperature limit settings
These are needed for temp1/2/3 related hwmon interfaces.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 06:48:03 +0000 (14:48 +0800)]
drm/amd/powerplay: correct Navi1X temperature limit settings
These are needed for temp1/2/3 related hwmon interfaces.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 3 Jul 2020 06:53:06 +0000 (14:53 +0800)]
drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount
The LCLK dpm table setup should be performed in .update_pcie_parameters().
Otherwise, the updated GenSpeed and LaneCount information will be lost.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 06:09:18 +0000 (14:09 +0800)]
drm/amd/powerplay: drop unnecessary wrapper around pcie parameters setting
This can also help to maintain clear code layer.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 04:42:06 +0000 (12:42 +0800)]
drm/amd/powerplay: drop unused APIs and parameters
Leftover of previous performance level setting cleanups.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 04:26:26 +0000 (12:26 +0800)]
drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper V2
By moving the implemention to renoir_ppt.c considering
it's really ASIC specific.
V2: fix compile warnings below
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:40:25: warning: array subscript is above array bounds [-Warray-bounds]
freq = table->FClocks[dpm_level].Freq; \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:46:25: warning: array subscript is above array bounds [-Warray-bounds]
freq = table->FClocks[dpm_level].Freq; \
drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’
GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 04:12:22 +0000 (12:12 +0800)]
drm/amd/powerplay: drop unnecessary wrappers
By calling the target APIs directly.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 10 Jul 2020 04:21:53 +0000 (12:21 +0800)]
drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICs
Before and after setting gfx clock soft max/min frequency.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 03:57:33 +0000 (11:57 +0800)]
drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_range
Use the common smu_v11_0_set_soft_freq_limited_range.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 03:32:58 +0000 (11:32 +0800)]
drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 03:26:53 +0000 (11:26 +0800)]
drm/amd/powerplay: drop unnecessary Navi1x specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 03:00:20 +0000 (11:00 +0800)]
drm/amd/powerplay: drop unnecessary Arcturus specific APIs
As a common performance level setting API is used. Then these
ASIC specific APIs are not needed any more.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Jul 2020 02:51:12 +0000 (10:51 +0800)]
drm/amd/powerplay: update the common API for performance level setting
So that it can be more widely shared around SMU v11 ASICs.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Preparing for coming code sharing around performance level
setting.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 10 Jun 2020 06:28:20 +0000 (14:28 +0800)]
drm/amd/powerplay: add new UMD pstate data structure
This is used to cache the clock frequencies for all UMD pstates.
So that we do not need to calculate from scratch on every UMD
pstate switch.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cache all clocks levels for every dpm table. They are needed
by other APIs.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Preparing for coming code sharing around performance level
setting.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 10 Jul 2020 02:46:48 +0000 (10:46 +0800)]
drm/amd/powerplay: implement a common set dpm table API for smu V11
Maximum the code sharing around smu V11.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 10 Jun 2020 06:32:58 +0000 (14:32 +0800)]
drm/amd/powerplay: add more members for dpm table
These members can help to cache the clock frequencies for all
dpm levels. Then simplifying the code for dpm level switching
is possible.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
If we are in RAS triggered situation and
BACO isn't support, emergency restart is needed,
and this code is only needed for some specific
cases(vega20 with given smu fw version).
After we add smu mode1 reset for sienna cichlid, we
need to share AMD_RESET_METHOD_MODE1 with psp mode1 reset,
so in amdgpu_device_gpu_recover, we need differentiate
which mode1 reset we are using, then decide if it's
a full reset and then decide if emergency restart is needed,
the logic will become much more complex.
After discussion with Hawking, move emergency restart logic
to an independent function.
drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr()
"u64 *wptr" points to the the wptr value in write back buffer and
"*wptr = (*wptr) >> 2;" results in the value being overwritten each time
when ->get_wptr() is called.
umr uses /sys/kernel/debug/dri/0/amdgpu_ring_sdma0 to get rptr/wptr and
decode ring content and it is affected by this issue.
fix and simplify the logic similar as sdma_v4_0_ring_get_wptr().
v2: fix for sdma5.2 as well
Suggested-by: Le Ma <le.ma@amd.com> Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
chen gong [Mon, 13 Jul 2020 08:11:24 +0000 (16:11 +0800)]
drm/amdgpu/powerplay: Modify SMC message name for setting power profile mode
I consulted Cai Land(Chuntian.Cai@amd.com), he told me corresponding smc
message name to fSMC_MSG_SetWorkloadMask() is
"PPSMC_MSG_ActiveProcessNotify" in firmware code of Renoir.
Strange though it may seem, but it's a fact.
Signed-off-by: chen gong <curry.gong@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Allow for vblank enabled with no active planes
[Why]
CRC capture doesn't work when the active plane count is 0 since we
currently tie both vblank and pageflip interrupts to active_plane_count
greater than 0.
[How]
The frontend is what generates the vblank interrupts while the backend
is what generates pageflip interrupts. Both have a requirement for
the CRTC to be active, so control the overall interrupt state based
on that instead.
Pageflip interrupts need to be enabled based on active plane count, but
we actually rely on power gating to take care of disabling the interrupt
for us on pipes that can be power gated.
For pipes that can't be power gated it's still fine to leave it enabled
since the interrupt only triggers after the address has been written
to that particular pipe - which we won't be doing without an active
plane.
The issue we had before with this setup was that we couldn't force
the state back on. We were essentially manipulating the refcount
to enable or disable as needed in a two pass approach.
However, there is a function that solves this problem more elegantly:
amdgpu_irq_update() will unconditionally call the set based on what it
thinks the current enablement state is.
This leaves two future TODO items for our IRQ handling:
- Disabling IRQs in commit tail instead of atomic commit
- Mapping the pageflip interrupt to VUPDATE or something that's tied to
the frontend instead of the backend since the mapping to CRTC is not
correct
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>