Evan Quan [Mon, 8 Jun 2020 09:33:03 +0000 (17:33 +0800)]
drm/amd/powerplay: correct power limit retrieving based on current power source
Instead of hard coding it as SMU_POWER_SOURCE_AC.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 8 Jun 2020 09:04:04 +0000 (17:04 +0800)]
drm/amd/powerplay: drop unused code around power limit
Drop unused APIs, variables and argument.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 8 Jun 2020 08:47:59 +0000 (16:47 +0800)]
drm/amd/powerplay: simplify the code around setting power limit
Use the cached max/current power limit and move the input check
to the top layer.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 8 Jun 2020 08:41:16 +0000 (16:41 +0800)]
drm/amd/powerplay: simplify the code around retrieving power limit
Use the cached max/current power limit for other cases except
.late_init.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 8 Jun 2020 08:29:41 +0000 (16:29 +0800)]
drm/amd/powerplay: maximize code sharing around power limit
Also cache the current and max power limits.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 8 Jun 2020 06:34:50 +0000 (14:34 +0800)]
drm/amd/powerplay: drop unnecessary get_pptable_power_limit wrappers
Minor code cleanup.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 5 Jun 2020 10:28:58 +0000 (18:28 +0800)]
drm/amd/powerplay: correct the APIs' naming
'UVD' is a HW engine name for Vega20 and before ASICs.
For newer ASICs, the similar engine is named as 'VCN'.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 5 Jun 2020 10:09:47 +0000 (18:09 +0800)]
drm/amd/powerplay: drop unnecessary wrappers
These APIs are used in amdgpu_smu.c only. Thus these wrappers
are unnecessary.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 5 Jun 2020 10:02:31 +0000 (18:02 +0800)]
drm/amd/powerplay: drop dead vce powergate code
This was for Vega20. However Vega20 support is
already dropped from current swSMU.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 5 Jun 2020 09:52:51 +0000 (17:52 +0800)]
drm/amd/powerplay: add error messages on some critical paths
Helpful for error diagnostic.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 5 Jun 2020 07:37:16 +0000 (15:37 +0800)]
drm/amd/powerplay: forbid to use pr_err/warn/info/debug
Use dev_err/warn/info/dbg instead. They are more MGPU friendly.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 5 Jun 2020 07:27:57 +0000 (15:27 +0800)]
drm/amd/powerplay: use MGPU friendly err/warn/info/dbg messages
Use dev_err/warn/info/dbg instead of pr_err/warn/info/debug.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Prike.Liang [Mon, 8 Jun 2020 07:20:56 +0000 (15:20 +0800)]
drm/amdgpu/soc15: fix nullptr issue in soc15_read_register() for reg base accessing
The failed case is no SDMA1 IP for Renoir discovery table while in accessing SDMA1 reg base,
thus need have nullptr test for soc15_read_register invoked in MMR addres space inquire opt.
Signed-off-by: Prike.Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 8 Jun 2020 19:39:33 +0000 (15:39 -0400)]
drm/amdgpu: skip BAR resizing if the bios already did it
No need to do it again.
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 08:27:13 +0000 (16:27 +0800)]
drm/amd/powerplay: use the same interval as PMFW on retrieving metrics table
Current 100ms interval makes no sense. User gets outdated
data due to this.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 10:28:34 +0000 (18:28 +0800)]
drm/amd/powerplay: update how to use metrics table on Sienna Cichlid
Retrieve only those data interested instead of the whole table.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 07:37:22 +0000 (15:37 +0800)]
drm/amd/powerplay: update how to use metrics table on Navi10
Retrieve only those data interested instead of the whole table.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 2 Jun 2020 09:48:11 +0000 (17:48 +0800)]
drm/amd/powerplay: update how to use metrics table on Arcturus
Retrieve only those interested metrics data instead of the whole
metrics table. By this, the memory copy can be dropped.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Fri, 5 Jun 2020 07:12:24 +0000 (15:12 +0800)]
drm/amd/display: drop duplicated .dsc_pg_control for dcn30
There're 2 .dsc_pg_control, drop the first one.
.dsc_pg_control = NULL,
.dsc_pg_control = dcn20_dsc_pg_control,
Signed-off-by: Flora Cui <flora.cui@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Fri, 5 Jun 2020 06:13:26 +0000 (14:13 +0800)]
drm/amd/display: drop duplicated structure
struct gpu_info_voltage_scaling_v1_0 & gpu_info_soc_bounding_box_v1_0 is
defined in amdgpu_socbb.h
Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 2 Jun 2020 08:29:08 +0000 (16:29 +0800)]
drm/amd/powerplay: move powerplay table operation out of smu_v11_0.c
move smu_v11_0_get_max_power_limit and smu_v11_0_set_thermal_range
function from smu_v11_0.c to asic specific _ppt.c to avoid powerplay
table conflict with different ASIC with smu11.
Evan Quan [Wed, 3 Jun 2020 03:45:49 +0000 (11:45 +0800)]
drm/amd/powerplay: use work queue to perform throttling logging
As IO operations(access to SMU internals) and possible sleep are
involved in throttling logging. Workqueue can handle them well.
Otherwise we may hit "scheduling while atomic" error.
Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 1 Jun 2020 10:31:20 +0000 (18:31 +0800)]
drm/amd/powerplay: skip BACO feature on DPMs disablement
Instead of disabling and reenabling it later.
Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 1 Jun 2020 06:03:57 +0000 (14:03 +0800)]
drm/amd/powerplay: add firmware cleanup on sw_fini
To avoid possible memory leak.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 1 Jun 2020 05:08:56 +0000 (13:08 +0800)]
drm/amd/powerplay: move amdgpu_irq_src to the smu structure allocation
Rather than allocating it dynamically at runtime considering it is only
several bytes in size.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 04:00:11 +0000 (12:00 +0800)]
drm/amd/powerplay: maximize code sharing between .hw_fini and .suspend
Thus redundant code can be dropped.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:50:39 +0000 (11:50 +0800)]
drm/amd/powerplay: better namings
And some minor changes as dropping unused parameter and label
internal used API as static.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:42:08 +0000 (11:42 +0800)]
drm/amd/powerplay: sort those operations performed in hw setup
Those common operations(for all ASICs) are placed first and followed
by ASIC specific ones. While the display related are placed at the last.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:35:45 +0000 (11:35 +0800)]
drm/amd/powerplay: maximize code sharing between .hw_init and .resume
Then redundant code can be dropped.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:25:28 +0000 (11:25 +0800)]
drm/amd/powerplay: move those operations not needed for resume out
Since smu_smc_table_hw_init() is needed for both .hw_init and .resume.
By doing this, we can drop unnecessary operations on resume.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:15:12 +0000 (11:15 +0800)]
drm/amd/powerplay: postpone operations not required for hw setup to late_init
So that we do not need to perform those unnecessary operations again on
resume.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 29 May 2020 06:07:41 +0000 (14:07 +0800)]
drm/amd/powerplay: clean up the overdrive settings
Eliminate the buffer allocation and drop the unnecessary
overdrive table uploading.
Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 28 May 2020 10:50:00 +0000 (18:50 +0800)]
drm/amd/powerplay: clean up the APIs for pptable setup
Combine and simplify the logics for setup pptable.
Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 28 May 2020 10:41:28 +0000 (18:41 +0800)]
drm/amd/powerplay: clean up the APIs for bootup clocks
Combine and simplify the logics for retrieving bootup
clocks.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 28 May 2020 08:55:08 +0000 (16:55 +0800)]
drm/amd/powerplay: centralize all buffer allocation in sw_init phase
To fit common design. And this can simplify the buffer deallocation.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 3 Jun 2020 10:09:01 +0000 (18:09 +0800)]
drm/amd/powerplay: implement a common API for dpms disablement
So that code can be shared between .hw_fini and .suspend.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 3 Jun 2020 10:06:02 +0000 (18:06 +0800)]
drm/amd/powerplay: drop unused APIs and unnecessary checks
Minor code cleanups.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 8 Jun 2020 22:05:34 +0000 (18:05 -0400)]
drm/amd/powerplay: eliminate asic type check
The macros check if the asic has the callback.
So no need to explicitly check.
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 2 Jun 2020 21:22:48 +0000 (17:22 -0400)]
drm/amdgpu/display: use blanked rather than plane state for sync groups
We may end up with no planes set yet, depending on the ordering, but we
should have the proper blanking state which is either handled by either
DPG or TG depending on the hardware generation. Check both to determine
the proper blanked state.
Bug: https://gitlab.freedesktop.org/drm/amd/issues/781 Fixes: 5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state") Cc: nicholas.kazlauskas@amd.com Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Revalidate bandwidth before commiting DC updates
[Why]
Whenever we switch between tiled formats without also switching pixel
formats or doing anything else that recreates the DC plane state we
can run into underflow or hangs since we're not updating the
DML parameters before committing to the hardware.
[How]
If the update type is FULL then call validate_bandwidth again to update
the DML parmeters before committing the state.
This is basically just a workaround and protective measure against
update types being added DC where we could run into this issue in
the future.
We can only fully validate the state in advance before applying it to
the hardware if we recreate all the plane and stream states since
we can't modify what's currently in use.
The next step is to update DM to ensure that we're creating the plane
and stream states for whatever could potentially be a full update in
DC to pre-emptively recreate the state for DC global validation.
The workaround can stay until this has been fixed in DM.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Only actually breakpoint if DEBUG_KERNEL_DC is enabled
To match previous behavior and to not hang the kernel if someone
accidentally builds with KGDB enabled.
Fixes: 1aad7078191116f ("drm/amd/display: Make BREAK_TO_DEBUGGER() a debug print") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 1 Jun 2020 02:51:34 +0000 (10:51 +0800)]
drm/amd/powerplay: use existed smu_dpm_set* interfaces to implement powergate functions
Abstract powergate_vcn/jpeg functions, using smu_dpm_set* to implement it.
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 22 May 2020 06:42:35 +0000 (14:42 +0800)]
drm/amdgpu: remove unnecessary check for mem train
a.Check whether mem train support when try to reserve related memory.
b.Remove ASIC check and atom firmware table version check as the check
of firmware capability is enough to achieve that purpose.
Likun Gao [Thu, 21 May 2020 02:33:15 +0000 (10:33 +0800)]
drm/amdgpu: reserve fb according to return value from vbios
Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards
for all the use cases (IP discovery/G6 memory
training/profiling/diagnostic data.etc), otherwise, fallback to legacy
approach to check and reserve tmr block for ip discovery data and G6
memory training data respectively
Likun Gao [Mon, 18 May 2020 10:44:10 +0000 (18:44 +0800)]
drm/amd/powerplay: drop sienna_cichlid hardcode of using pptable
Drop the hardcode of sienna_cichlid which will force to use softpptable,
so that it can use pptable on vbios once the value of pp_table_id get
from vbios is 0.