From 364a54742f569b7221f0022594ef3d8384a8517c Mon Sep 17 00:00:00 2001 From: Jian J Wang Date: Thu, 7 Dec 2017 20:14:35 +0800 Subject: [PATCH] MdePkg/BaseLib: Add stack switch related definitions for IA32 The new definitions include two structures IA32_TASK_STATE_SEGMENT IA32_TSS_DESCRIPTOR two macros IA32_GDT_TYPE_TSS IA32_GDT_ALIGNMENT and one API VOID EFIAPI AsmWriteTr ( IN UINT16 Selector ); They're needed to setup task gate and interrupt stack table for stack switch. Cc: Michael D Kinney Cc: Liming Gao Cc: Jiewen Yao Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan Reviewed-by: Jiewen.yao@intel.com --- MdePkg/Include/Library/BaseLib.h | 117 +++++++++++++++++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 3 + MdePkg/Library/BaseLib/Ia32/WriteTr.nasm | 36 +++++++ MdePkg/Library/BaseLib/X64/WriteTr.nasm | 37 +++++++ 4 files changed, 193 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteTr.nasm create mode 100644 MdePkg/Library/BaseLib/X64/WriteTr.nasm diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index d33c3b6b38..2b98af4cd1 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -6647,6 +6647,8 @@ typedef struct { #define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E #define IA32_IDT_GATE_TYPE_TRAP_32 0x8F +#define IA32_GDT_TYPE_TSS 0x9 +#define IA32_GDT_ALIGNMENT 8 #if defined (MDE_CPU_IA32) /// @@ -6663,6 +6665,70 @@ typedef union { UINT64 Uint64; } IA32_IDT_GATE_DESCRIPTOR; +#pragma pack (1) +// +// IA32 Task-State Segment Definition +// +typedef struct { + UINT16 PreviousTaskLink; + UINT16 Reserved_2; + UINT32 ESP0; + UINT16 SS0; + UINT16 Reserved_10; + UINT32 ESP1; + UINT16 SS1; + UINT16 Reserved_18; + UINT32 ESP2; + UINT16 SS2; + UINT16 Reserved_26; + UINT32 CR3; + UINT32 EIP; + UINT32 EFLAGS; + UINT32 EAX; + UINT32 ECX; + UINT32 EDX; + UINT32 EBX; + UINT32 ESP; + UINT32 EBP; + UINT32 ESI; + UINT32 EDI; + UINT16 ES; + UINT16 Reserved_74; + UINT16 CS; + UINT16 Reserved_78; + UINT16 SS; + UINT16 Reserved_82; + UINT16 DS; + UINT16 Reserved_86; + UINT16 FS; + UINT16 Reserved_90; + UINT16 GS; + UINT16 Reserved_94; + UINT16 LDTSegmentSelector; + UINT16 Reserved_98; + UINT16 T; + UINT16 IOMapBaseAddress; +} IA32_TASK_STATE_SEGMENT; + +typedef union { + struct { + UINT32 LimitLow:16; ///< Segment Limit 15..00 + UINT32 BaseLow:16; ///< Base Address 15..00 + UINT32 BaseMid:8; ///< Base Address 23..16 + UINT32 Type:4; ///< Type (1 0 B 1) + UINT32 Reserved_43:1; ///< 0 + UINT32 DPL:2; ///< Descriptor Privilege Level + UINT32 P:1; ///< Segment Present + UINT32 LimitHigh:4; ///< Segment Limit 19..16 + UINT32 AVL:1; ///< Available for use by system software + UINT32 Reserved_52:2; ///< 0 0 + UINT32 G:1; ///< Granularity + UINT32 BaseHigh:8; ///< Base Address 31..24 + } Bits; + UINT64 Uint64; +} IA32_TSS_DESCRIPTOR; +#pragma pack () + #endif #if defined (MDE_CPU_X64) @@ -6685,6 +6751,46 @@ typedef union { } Uint128; } IA32_IDT_GATE_DESCRIPTOR; +#pragma pack (1) +// +// IA32 Task-State Segment Definition +// +typedef struct { + UINT32 Reserved_0; + UINT64 RSP0; + UINT64 RSP1; + UINT64 RSP2; + UINT64 Reserved_28; + UINT64 IST[7]; + UINT64 Reserved_92; + UINT16 Reserved_100; + UINT16 IOMapBaseAddress; +} IA32_TASK_STATE_SEGMENT; + +typedef union { + struct { + UINT32 LimitLow:16; ///< Segment Limit 15..00 + UINT32 BaseLow:16; ///< Base Address 15..00 + UINT32 BaseMidl:8; ///< Base Address 23..16 + UINT32 Type:4; ///< Type (1 0 B 1) + UINT32 Reserved_43:1; ///< 0 + UINT32 DPL:2; ///< Descriptor Privilege Level + UINT32 P:1; ///< Segment Present + UINT32 LimitHigh:4; ///< Segment Limit 19..16 + UINT32 AVL:1; ///< Available for use by system software + UINT32 Reserved_52:2; ///< 0 0 + UINT32 G:1; ///< Granularity + UINT32 BaseMidh:8; ///< Base Address 31..24 + UINT32 BaseHigh:32; ///< Base Address 63..32 + UINT32 Reserved_96:32; ///< Reserved + } Bits; + struct { + UINT64 Uint64; + UINT64 Uint64_1; + } Uint128; +} IA32_TSS_DESCRIPTOR; +#pragma pack () + #endif /// @@ -8950,6 +9056,17 @@ AsmRdRand64 ( OUT UINT64 *Rand ); +/** + Load given selector into TR register + + @param[in] Selector Task segment selector +**/ +VOID +EFIAPI +AsmWriteTr ( + IN UINT16 Selector + ); + #endif #endif diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 320ac457ea..fbfb0063b7 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -67,6 +67,8 @@ BaseLibInternals.h [Sources.Ia32] + Ia32/WriteTr.nasm + Ia32/Wbinvd.c | MSFT Ia32/WriteMm7.c | MSFT Ia32/WriteMm6.c | MSFT @@ -447,6 +449,7 @@ X64/EnableCache.asm X64/DisableCache.nasm X64/DisableCache.asm + X64/WriteTr.nasm X64/CpuBreakpoint.c | MSFT X64/WriteMsr64.c | MSFT diff --git a/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm b/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm new file mode 100644 index 0000000000..cde5a3a423 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/WriteTr.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------ ; +; Copyright (c) 2017, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Module Name: +; +; WriteTr.nasm +; +; Abstract: +; +; Write TR register +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; AsmWriteTr ( +; UINT16 Selector +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteTr) +ASM_PFX(AsmWriteTr): + mov eax, [esp+4] + ltr ax + ret + diff --git a/MdePkg/Library/BaseLib/X64/WriteTr.nasm b/MdePkg/Library/BaseLib/X64/WriteTr.nasm new file mode 100644 index 0000000000..3bf1500c36 --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/WriteTr.nasm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------ ; +; Copyright (c) 2017, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Module Name: +; +; WriteTr.nasm +; +; Abstract: +; +; Write TR register +; +; Notes: +; +;------------------------------------------------------------------------------ + + DEFAULT REL + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; AsmWriteTr ( +; UINT16 Selector +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmWriteTr) +ASM_PFX(AsmWriteTr): + mov eax, ecx + ltr ax + ret + -- 2.39.2