From e9415e4846dd8e93c5cabff66e3d599a7844a740 Mon Sep 17 00:00:00 2001 From: Jian J Wang Date: Thu, 7 Dec 2017 20:16:29 +0800 Subject: [PATCH] UefiCpuPkg/MpLib: Add GDTR, IDTR and TR in saved AP data In current implementation of CPU MP service, AP is initialized with data copied from BSP. Stack switch required by Stack Guard feature needs different GDT, IDT table and task gates for each logic processor. This patch adds GDTR, IDTR and TR into structure CPU_VOLATILE_REGISTERS and related code in save and restore methods. This can make sure that any changes to GDT, IDT and task gate for an AP will be kept from overwritten by BSP settings. Cc: Eric Dong Cc: Laszlo Ersek Cc: Jiewen Yao Suggested-by: Ayellet Wolman Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Jeff Fan Reviewed-by: Jiewen.yao@intel.com --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 17 +++++++++++++++++ UefiCpuPkg/Library/MpInitLib/MpLib.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 61b14c9843..0c2058a7b0 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -195,6 +195,10 @@ SaveVolatileRegisters ( VolatileRegisters->Dr6 = AsmReadDr6 (); VolatileRegisters->Dr7 = AsmReadDr7 (); } + + AsmReadGdtr (&VolatileRegisters->Gdtr); + AsmReadIdtr (&VolatileRegisters->Idtr); + VolatileRegisters->Tr = AsmReadTr (); } /** @@ -211,6 +215,7 @@ RestoreVolatileRegisters ( ) { CPUID_VERSION_INFO_EDX VersionInfoEdx; + IA32_TSS_DESCRIPTOR *Tss; AsmWriteCr0 (VolatileRegisters->Cr0); AsmWriteCr3 (VolatileRegisters->Cr3); @@ -231,6 +236,18 @@ RestoreVolatileRegisters ( AsmWriteDr7 (VolatileRegisters->Dr7); } } + + AsmWriteGdtr (&VolatileRegisters->Gdtr); + AsmWriteIdtr (&VolatileRegisters->Idtr); + if (VolatileRegisters->Tr != 0 && + VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) { + Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base + + VolatileRegisters->Tr); + if (Tss->Bits.P == 1) { + Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case + AsmWriteTr (VolatileRegisters->Tr); + } + } } /** diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index d13d5c06f5..685e96cbac 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -102,6 +102,9 @@ typedef struct { UINTN Dr3; UINTN Dr6; UINTN Dr7; + IA32_DESCRIPTOR Gdtr; + IA32_DESCRIPTOR Idtr; + UINT16 Tr; } CPU_VOLATILE_REGISTERS; // -- 2.39.2