From 6820588efa4fbab9ab6f0457f2c83c3bc7498ae3 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 9 Mar 2021 12:01:28 +0100 Subject: [PATCH] hw/arm: ast2600: Correct the iBT interrupt ID MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The AST2600 allocates distinct GIC IRQs for the LPC subdevices such as the iBT device. Previously on the AST2400 and AST2500 the LPC subdevices shared a single LPC IRQ. Signed-off-by: Andrew Jeffery Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-Id: <20210302014317.915120-4-andrew@aj.id.au> Signed-off-by: Cédric Le Goater --- hw/arm/aspeed_ast2600.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 1dc56ce478..7635d4bae9 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -98,7 +98,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_DEV_WDT] = 24, [ASPEED_DEV_PWM] = 44, [ASPEED_DEV_LPC] = 35, - [ASPEED_DEV_IBT] = 35, /* LPC */ + [ASPEED_DEV_IBT] = 143, [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ [ASPEED_DEV_ETH1] = 2, [ASPEED_DEV_ETH2] = 3, -- 2.39.2